Texas Instruments TMS320DM6467CCUTAV
- Part No.:
- TMS320DM6467CCUTAV
- Manufacturer:
- Texas Instruments
- Category:
- DSP (Digital Signal Processors)
- Package:
- 529-BFBGA, FCBGA
- Datasheet:
-
TMS320DM6467CCUTAV.pdf
- Description:
- IC DGTL MEDIA SOC 529FCBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TMS320DM6467CCUTAV from Texas Instruments is a dual-core digital media system-on-chip (SoC) integrating a 729-MHz TMS320C64x+ DSP core and a 364.5-MHz ARM926EJ-S RISC processor, with 128KB L2 unified RAM/cache, dual HDVICP video co-processors, and 529-pin Pb-free BGA (CUT) packaging. It delivers 5832 C64x+ MIPS for real-time H.264/MPEG4/VC1 encode/decode in networked video infrastructure.
For engineers reviewing the TMS320DM6467CCUTAV datasheet, TMS320DM6467CCUTAV pinout, TMS320DM6467CCUTAV application, or TMS320DM6467CCUTAV equivalent, key selection criteria include DDR2 memory controller timing (310.5 MHz), dual HDVICP hardware acceleration support, VPIF video port bandwidth (108 MHz), and industrial temperature grade (-40°C to +85°C) compliance.
Technical Context
The TMS320DM6467CCUTAV implements a tightly coupled dual-processor architecture where the ARM926EJ-S handles OS management, peripheral control, and boot sequencing while the C64x+ DSP executes compute-intensive video algorithms. Its L1/L2 memory hierarchy includes 32KB L1P (direct-mapped), 32KB L1D (2-way set-associative), and 128KB configurable L2 RAM/cache.
Hardware accelerators include two independent HDVICP engines supporting H.264 Baseline/Main/High Profile decode and MPEG-4 SP/ASP encode/decode, plus a Video Data Conversion Engine (VDCE) for chroma conversion (4:2:2 ↔ 4:2:0) and horizontal/vertical downscaling - all operating without DSP core intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| DSP Core | TMS320C64x+ at 729 MHz: enables 5832 MIPS for real-time video analytics and multi-stream encoding |
| ARM Core | ARM926EJ-S at 364.5 MHz: supports Linux/Windows CE with MMU, Jazelle Java acceleration, and embedded trace |
| Memory Architecture | 32KB L1P + 32KB L1D + 128KB L2 unified RAM/cache: balances low-latency access and shared bandwidth for mixed workloads |
| Video Acceleration | Dual HDVICP engines: offload H.264, MPEG2, VC1, MPEG4 SP/ASP encode/decode, freeing >80% of DSP cycles |
| Video Interface | 99-/108-MHz VPIF with BT.656/BT.1120/raw capture/display: supports dual SD or single HD video I/O paths |
| External Memory | 297-/310.5-MHz 32-bit DDR2 SDRAM controller + asynchronous EMIFA: enables high-bandwidth frame buffering and NAND/NOR boot |
| Package | 529-pin Pb-free BGA (CUT), 19 × 19 mm, 0.8-mm ball pitch: compatible with industrial PCB assembly standards |
Pinout & Package
529-pin Pb-free BGA (CUT) package with 0.8-mm ball pitch, 19 × 19 mm body size, and thermal pad exposed on underside per TI SZZA012B package drawing.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| DEV_CLKIN | Main oscillator input | Accepts 27-MHz crystal or clock source; feeds PLLC1 for DSP/ARM clock generation |
| VDD_DSP | DSP core power supply | 1.05-V or 1.2-V adaptive supply; voltage selected by SmartReflex-compatible configuration |
| VDD_ARM | ARM core power supply | 1.05-V or 1.2-V adaptive supply; independently regulated from DSP domain |
| VDD_IO | I/O bank power | 1.8-V and 3.3-V banks separately configurable; supports mixed-voltage interface design |
| EMIF_A[0:22] | DDR2 address bus | 23-bit address lines for 512MB DDR2 space; timing-critical routing required for 310.5-MHz operation |
| VPIF_VD[0:15] | Video data bus | 16-bit parallel video data path for BT.1120 HD capture/display; requires matched-length traces |
| TSIF_DATA[0:7] | Transport stream data | 8-bit parallel MPEG-TS input/output; synchronized to CRGEN-generated clock for jitter tolerance |
Key Features
| Feature | Design Value |
|---|---|
| Dual HDVICP hardware accelerators | Enable concurrent H.264 Main Profile decode + MPEG4 ASP encode without DSP core load |
| Configurable VPIF with BT.656/BT.1120 support | Allows flexible SD/HD video I/O mapping - e.g., one 8-bit BT.656 capture + one 16-bit BT.1120 display simultaneously |
| 32-bit DDR2 SDRAM controller (310.5 MHz) | Delivers 4.97 GB/s peak bandwidth for multi-channel HD frame buffers and streaming applications |
| ARM926EJ-S with ETB11™ debug buffer | 4KB on-chip trace memory enables non-intrusive real-time instruction/data flow analysis during video pipeline debugging |
| SmartReflex™-compatible voltage scaling | Dynamic core voltage adjustment (1.05 V / 1.2 V) reduces active power by up to 30% under variable workload conditions |
Applications
| IP Video Surveillance Encoder | Networked Digital Signage Player |
|---|---|
Use Scenario: Real-time encoding of four 720p30 video streams from analog cameras into H.264 for IP transmission over Gigabit Ethernet. IC Role / Device Role / Timing Role: TMS320DM6467CCUTAV acts as the central media processing unit, coordinating VPIF capture, HDVICP encode, DDR2 frame buffering, and EMAC packetization. Use Value: Dual HDVICP engines enable simultaneous encode of all four streams at full resolution without external FPGA assistance. | Use Scenario: Local playback and dynamic overlay of HD video content (1080p60) on commercial displays via HDMI, with network-based playlist updates. IC Role / Device Role / Timing Role: TMS320DM6467CCUTAV serves as the media engine, decoding MPEG4/H.264 assets from NAND flash, applying VDCE chroma conversion, and driving VPIF output to HDMI transmitter. Use Value: Integrated VDCE eliminates need for external video format converter ICs when interfacing with 4:2:0 decoded content and 4:4:4 HDMI sinks. |
| Video Conferencing Endpoint | Industrial Video Infrastructure Node |
Use Scenario: Full-duplex HD video conferencing with local echo cancellation, speaker tracking, and dual-stream (main/presentation) encoding. IC Role / Device Role / Timing Role: TMS320DM6467CCUTAV hosts ARM-based SIP stack and UI, while C64x+ DSP runs real-time audio/video algorithms and HDVICP handles dual H.264 encode/decode pipelines. Use Value: 5832 MIPS DSP performance ensures sub-100ms end-to-end latency for interactive video collaboration. | Use Scenario: Centralized video transcoding node converting legacy MPEG2 transport streams to adaptive H.264/AAC for OTT delivery. IC Role / Device Role / Timing Role: TMS320DM6467CCUTAV functions as a dedicated transcoder, using TSIF modules for input stream ingestion and HDVICP + C64x+ for re-encoding with bitrate control. Use Value: Two TSIF interfaces allow simultaneous acquisition of primary and backup transport streams with independent CRGEN clock recovery. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital media SoC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TMS320DM6467ZUT | Same silicon, 529-pin ZUT PBGA package (lead-based, obsolete); no SmartReflex support; rated only for commercial temp (0°C to 70°C) | Lacks industrial temperature rating and adaptive voltage scaling; incompatible with Pb-free manufacturing | Select TMS320DM6467CCUTAV for new designs requiring RoHS compliance and extended temperature operation. |
| TI DM8168 | Successor SoC with Cortex-A8 + C674x DSP, 1080p60 decode, SATA, PCIe; higher power, larger BGA (684-pin) | Supports newer codecs (HEVC), higher resolution, and faster interconnects but requires board redesign | Choose DM8168 only when upgrading beyond H.264 Main Profile or requiring SATA storage integration. |
Compared with TMS320DM6467ZUT, the TMS320DM6467CCUTAV adds SmartReflex power management and industrial temp support; compared with DM8168, it offers lower system cost and simpler layout at the expense of HEVC and PCIe capability.
Availability
TMS320DM6467CCUTAV is available at Aetrix Electronics and suitable for IP video surveillance encoders, networked digital signage players, video conferencing endpoints, and industrial video infrastructure nodes requiring stable component supply across extended product lifecycles.
Supply support for TMS320DM6467CCUTAV includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, delivering analog and embedded processing solutions for industrial, automotive, and communications markets.
The DaVinci™ digital media SoC product line - including the TMS320DM6467CCUTAV - was engineered specifically for real-time video encode/decode/transcode in resource-constrained embedded systems with integrated OS support and hardware-accelerated multimedia pipelines.
FAQ
What is the maximum DDR2 memory bandwidth supported by the TMS320DM6467CCUTAV?
The TMS320DM6467CCUTAV supports a 310.5-MHz DDR2 SDRAM controller with a 32-bit bus width, delivering a theoretical peak bandwidth of 4.97 GB/s. This bandwidth is sufficient for dual-channel 720p60 video frame buffering and real-time HD processing. The controller complies with JEDEC DDR2-667/800 specifications and supports programmable timing parameters for optimization across memory vendors.
Does the TMS320DM6467CCUTAV support H.264 High Profile encoding?
No, the TMS320DM6467CCUTAV's dual HDVICP engines support H.264 Baseline and Main Profiles for both encode and decode, but not High Profile. High Profile features such as B-frames, CABAC entropy coding, and 8×8 transform are not implemented in the fixed-function HDVICP hardware. For High Profile support, TI recommends migrating to the DM8168 or later DaVinci generations.
What boot sources are natively supported by the TMS320DM6467CCUTAV?
The TMS320DM6467CCUTAV supports multiple boot modes via its on-chip ARM ROM bootloader (RBL), including NAND flash (8-/16-bit), NOR flash (8-/16-bit), UART, and EMIFA-connected peripherals. Boot configuration is selected using GPIO strap pins at reset. The RBL initializes clocks, PLLs, and memory controllers before loading the second-stage bootloader from the selected medium.
How many independent video capture channels does the TMS320DM6467CCUTAV support via VPIF?
The TMS320DM6467CCUTAV supports up to two independent 8-bit BT.656 video capture channels, or one 16-bit BT.1120 HD capture channel, or one raw video capture channel (8-/10-/12-bit). These configurations are mutually exclusive per VPIF instance; the device contains one VPIF module with flexible pin multiplexing, not multiple physical ports.
Is the TMS320DM6467CCUTAV pin-compatible with other DM6467 variants like the ZUT package?
No, the TMS320DM6467CCUTAV (CUT package) is not pin-compatible with the legacy ZUT package despite identical pin count (529). Ball map, power sequencing requirements, and thermal pad configuration differ between CUT (Pb-free, 0.8-mm pitch) and ZUT (lead-based, 1.0-mm pitch) packages. Migration requires PCB redesign and validation per TI SZZA012B and SZZA009 package drawings.
TMS320DM6467CCUTAV Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- TMS320DM646x, DaVinci™
- Package/Case:
- 529-BFBGA, FCBGA
- Packaging:
- Tray
- Product Status:
- Not For New Designs
- Type:
- Digital Media System-on-Chip (DMSoC)
- Interface:
- EBI/EMI, Ethernet, HPI, I2C, McASP, PCI, SPI, UART, USB
- Clock Rate:
- 594MHz DSP, 297MHz ARM®
- Non-Volatile Memory:
- ROM (8kB)
- On-Chip RAM:
- 248kB
- Voltage - I/O:
- 1.8V, 3.3V
- Voltage - Core:
- 1.05V, 1.20V
- Operating Temperature:
- -40°C ~ 105°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 529-FCBGA (19x19)
TMS320DM6467CCUTAV FAQ
1.How can I place an order for TMS320DM6467CCUTAV through Aetrix?
Please submit a Request for Quotation (RFQ) for TMS320DM6467CCUTAV on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TMS320DM6467CCUTAV reliable?
The price and inventory of TMS320DM6467CCUTAV are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TMS320DM6467CCUTAV is usually 5 days.
3.What payment methods are accepted for TMS320DM6467CCUTAV?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TMS320DM6467CCUTAV transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TMS320DM6467CCUTAV?
TMS320DM6467CCUTAV orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TMS320DM6467CCUTAV order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TMS320DM6467CCUTAV?
For technical support, including TMS320DM6467CCUTAV datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TMS320DM6467CCUTAV requirements.
6.How does Aetrix verify that TMS320DM6467CCUTAV is sourced from the original manufacturer or authorized distributors?
All TMS320DM6467CCUTAV products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TMS320DM6467CCUTAV meets industry standards.
7.What is the process for return or replacement of TMS320DM6467CCUTAV?
All TMS320DM6467CCUTAV units undergo pre-shipment inspection (PSI). If there is an issue with TMS320DM6467CCUTAV, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TMS320DM6467CCUTAV part is unused and in its original packaging.
Return procedure for TMS320DM6467CCUTAV:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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