My Inquiry
My Account
Texas Instruments TMS320DM6467TCUTD1
- Part No.:
- TMS320DM6467TCUTD1
- Manufacturer:
- Texas Instruments
- Category:
- DSP (Digital Signal Processors)
- Package:
- 529-BFBGA, FCBGA
- Datasheet:
-
TMS320DM6467TCUTD1.pdf
- Description:
- IC DGTL MEDIA SOC 529FCBGA
- Quantity:
- Payment:
- Shipping:
Inventory:2,988
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TMS320DM6467TCUTD1 from Texas Instruments is a dual-core digital media system-on-chip (SoC) integrating a 1-GHz TMS320C64x+ DSP and a 500-MHz ARM926EJ-S RISC processor, with 128KB L2 unified RAM/cache, dual HDVICP video co-processors, and 150-MHz configurable video port interface (VPIF). It targets high-throughput video encode/decode/transcode in networked media infrastructure and embedded imaging systems.
For engineers reviewing the TMS320DM6467TCUTD1 datasheet, TMS320DM6467TCUTD1 pinout, TMS320DM6467TCUTD1 application, or TMS320DM6467TCUTD1 equivalent, key selection criteria include DDR2 memory controller support (up to 400 MHz), dual transport stream interface (TSIF) modules with PID filtering, H.264/MPEG4/VC1 codec acceleration, and industrial-temperature-rated 529-pin Pb-free BGA (CUT) packaging.
Technical Context
The TMS320DM6467TCUTD1 implements a tightly coupled heterogeneous architecture where the ARM926EJ-S handles OS services, peripheral control, and system boot while the C64x+ DSP executes real-time video signal processing at 8000 MIPS. Its memory subsystem features separate 16KB instruction and 8KB data caches for ARM, plus 32KB L1P/L1D and 128KB unified L2 RAM/cache with flexible allocation.
Hardware acceleration includes two independent HDVICP engines supporting H.264 Baseline/Main/High Profile decode and encode, VDCE for chroma conversion (4:2:2 ↔ 4:2:0) and downscaling, and CRGEN modules for synchronized clock recovery from MPEG transport streams - all accessible via EDMA3 with 64 independent channels and 8 QDMA channels.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core(s) | Dual-core: 1-GHz C64x+ DSP + 500-MHz ARM926EJ-S, enabling concurrent real-time video processing and Linux-based system management. |
| L2 Memory | 128KB unified mapped RAM/cache, configurable as full RAM, full cache, or split allocation - critical for low-latency frame buffering in HD video pipelines. |
| Video Acceleration | Dual HDVICP engines supporting H.264, MPEG2, VC1, MPEG4 SP/ASP encode/decode - offloads >90% of motion estimation and entropy coding from DSP core. |
| Memory Interface | DDR2 SDRAM controller up to 400 MHz (32-bit bus); asynchronous EMIFA for NOR/NAND flash - enables boot-from-NAND and high-bandwidth streaming buffer storage. |
| Video I/O | 150-MHz VPIF with dual 8-bit BT.656 capture/display or single 16-bit BT.1120 HD interface - supports simultaneous SD/HD video ingest and output without external glue logic. |
| Transport Stream | Two TSIF modules: one parallel/serial with PID filter (7 tables), one serial-only - enables direct demuxing of broadcast MPEG-TS streams with hardware timestamp alignment. |
| Package | 529-pin Pb-free BGA (CUT suffix), 19 × 19 mm, 0.8-mm ball pitch - industrial-temperature rated (–40°C to +85°C) and compatible with standard PCB assembly processes. |
| Power | 1.3-V core / 1.8-V & 3.3-V I/O - supports dynamic voltage/frequency scaling per subsystem to meet thermal constraints in fanless enclosures. |
Pinout & Package
529-pin Pb-free BGA (CUT package), 0.8-mm ball pitch, 19 × 19 mm body size. Pin functions defined per TI SPRS605C datasheet Section 3.6 (Pin Assignments) and Section 3.7 (Terminal Functions).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| DEV_CLKIN | Main oscillator input | Accepts 27–35 MHz crystal or clock source; feeds PLLC1/PLLC2 for generating 1-GHz DSP and 500-MHz ARM clocks. |
| VDD_CORE | Core power supply | 1.3-V regulated supply for C64x+ and ARM926EJ-S cores; requires low-noise decoupling due to high transient current during video processing bursts. |
| VDD_IO_18 | 1.8-V I/O bank | Powers DDR2 DQ/DQS, VPIF, TSIF, and McASP interfaces - matches JEDEC SSTL_18 signaling for reliable high-speed memory/video timing. |
| VDD_IO_33 | 3.3-V I/O bank | Supplies EMAC, PCI, HPI, SPI, UART, and GPIO - enables direct interfacing with legacy industrial peripherals and Ethernet PHYs. |
| EMU0–EMU3 | JTAG emulation pins | IEEE-1149.1 boundary-scan interface for real-time debugging of both ARM and DSP subsystems using XDS560-class emulators. |
| GPIO[0:32] | General-purpose I/O | 33 multiplexed pins supporting interrupt/event generation; used for board-level status signaling, reset coordination, and FPGA configuration handshaking. |
Key Features
| Feature | Design Value |
|---|---|
| Dual HDVICP Engines | Enables simultaneous H.264 encode + decode at 1080p30, freeing ~70% of C64x+ MIPS for analytics or multi-stream handling. |
| VDCE Hardware Block | Performs real-time horizontal/vertical downscaling and 4:2:2 ↔ 4:2:0 chroma conversion without CPU/DSP intervention - reduces memory bandwidth by 50% in multi-format transcoding. |
| CRGEN Modules | Two dedicated clock recovery generators synchronize system timebase to incoming MPEG-TS packet timestamps - eliminates audio/video drift in broadcast reception systems. |
| EDMA3 Controller | 64-channel DMA with QDMA support enables zero-CPU video frame transfers between DDR2, VPIF, HDVICP, and TSIF - sustains 1.2 GB/s sustained throughput across multiple concurrent streams. |
| ARM ROM Bootloader (RBL) | On-chip 8KB ROM provides secure, fail-safe boot from NAND, UART, or EMAC - eliminates need for external boot PROM and accelerates production programming. |
| Flexible Power Management | Independent PSC-controlled clock gating for 30+ peripherals and dynamic voltage scaling for ARM/DSP domains - achieves sub-500mW idle power in surveillance DVR standby mode. |
Applications
| IP Video Encoder | Network DVR |
|---|---|
Use Scenario: Real-time encoding of analog camera feeds (CVBS or Y/C) into H.264 streams for IP transmission over Gigabit Ethernet. IC Role / Device Role / Timing Role: TMS320DM6467TCUTD1 acts as the central media processor - ingesting raw video via VPIF, compressing via HDVICP, and packetizing via EMAC with hardware timestamping. Use Value: Achieves 16-channel 720p30 encode at <2.5W total SoC power, eliminating need for active cooling in compact edge enclosures. | Use Scenario: Multi-stream recording and playback of HD video from IP cameras with local RAID storage and remote RTSP access. IC Role / Device Role / Timing Role: TMS320DM6467TCUTD1 manages ATA/ATAPI-6 HDD interface, decodes stored streams via HDVICP, and transcodes on-the-fly for mobile clients using VDCE-resized frames. Use Value: Enables simultaneous record/playback of four 1080p streams while maintaining <50ms end-to-end latency for live preview. |
| Broadcast STB Transcoder | Video Conferencing Bridge |
Use Scenario: Ingesting MPEG-TS broadcast signals via TSIF, decrypting conditional access, and re-encoding for adaptive bitrate delivery to OTT platforms. IC Role / Device Role / Timing Role: TMS320DM6467TCUTD1 performs PID filtering, PCR correction via CRGEN, and multi-profile H.264 encode using both HDVICP engines in parallel. Use Value: Supports 4K-to-1080p transrate with HDR metadata preservation and <1-frame A/V sync error across all output bitrates. | Use Scenario: Multipoint video mixing and transcoding for SIP/H.323 conferencing systems with mixed-resolution endpoints. IC Role / Device Role / Timing Role: TMS320DM6467TCUTD1 receives multiple RTP streams, resizes via VDCE, color-space converts, and re-encodes with dynamic GOP control per participant. Use Value: Delivers consistent 720p30 output to all participants regardless of input resolution, with <80ms total pipeline latency including jitter buffering. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital media SoC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TMS320DM6467ZUTD1 | Same silicon revision and feature set, but packaged in legacy ZUT (Pb-based) 529-pin BGA - obsolete per TI PDN dated 2012. | Not suitable for new designs requiring RoHS compliance or long-term supply continuity. | Select TMS320DM6467TCUTD1 for all new designs requiring Pb-free manufacturing and TI's current production support. |
| i.MX6Q | ARM Cortex-A9 quad-core (1 GHz), no integrated DSP or HDVICP; relies on GPU/VPU for video acceleration - lower deterministic latency for real-time encode. | Better suited for Android/Linux GUI-rich applications; lacks native MPEG-TS/CRGEN/TSIF for broadcast infrastructure. | Choose i.MX6Q only when application prioritizes general-purpose compute and multimedia APIs over hard real-time video pipeline determinism. |
Compared with TMS320DM6467ZUTD1, the TMS320DM6467TCUTD1 offers identical functionality with RoHS-compliant packaging and ongoing TI production support; versus i.MX6Q, it delivers superior deterministic video processing throughput and broadcast-specific peripherals - making it the preferred choice for carrier-grade media gateways and professional AV equipment.
Availability
TMS320DM6467TCUTD1 is available at Aetrix Electronics and suitable for IP video encoder, network DVR, broadcast STB transcoder, and video conferencing bridge applications requiring stable component supply, long-lifecycle assurance, and industrial-temperature operation.
Supply support for TMS320DM6467TCUTD1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, delivering analog and embedded processing solutions for industrial, automotive, personal electronics, and communications markets.
The TMS320DM6467TCUTD1 belongs to TI's DaVinci™ digital media SoC product line, engineered specifically for high-performance, low-power video infrastructure applications requiring hardware-accelerated encode/decode, transport stream handling, and real-time deterministic processing.
FAQ
What is the maximum DDR2 memory speed supported by the TMS320DM6467TCUTD1?
The TMS320DM6467TCUTD1 supports DDR2 SDRAM up to 400 MHz (200 MHz clock with double-data-rate), providing a theoretical peak bandwidth of 3.2 GB/s on its 32-bit bus. This speed is validated under industrial temperature conditions (–40°C to +85°C) and requires proper PCB layout adherence to TI's DDR2 routing guidelines in SPRS605C Section 7.10.
Does the TMS320DM6467TCUTD1 support H.264 High Profile encoding?
Yes, the TMS320DM6467TCUTD1 supports H.264 High Profile encoding through its dual HDVICP engines, as confirmed in TI SPRS605C Section 1.1 and Application Report SPRAB77. Each HDVICP engine handles baseline/main profile operations, and coordinated use enables High Profile features including B-frames, CABAC entropy coding, and 8×8 transform - subject to firmware version and configuration.
How many independent video capture channels does the TMS320DM6467TCUTD1 support simultaneously?
The TMS320DM6467TCUTD1 supports up to two independent 8-bit BT.656 video capture channels via its VPIF, or one 16-bit BT.1120 HD capture channel, or one 8-/10-/12-bit raw video capture channel - but not all concurrently. The VPIF is a shared resource with fixed bandwidth; simultaneous use of multiple capture modes requires time-division multiplexing controlled by the ARM subsystem.
Is USB 2.0 Host functionality available on the TMS320DM6467TCUTD1?
Yes, the TMS320DM6467TCUTD1 integrates a full-featured USB 2.0 PHY supporting high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) host operation with mini-host capability for one external device. This is confirmed in SPRS605C Section 1.1 and Section 7.19, and applies to all -1G silicon revisions dated May 1, 2010 or later.
What boot sources are supported by the on-chip ROM bootloader (RBL) of the TMS320DM6467TCUTD1?
The TMS320DM6467TCUTD1 RBL supports boot from NAND flash (8-/16-bit), UART (with XMODEM protocol), EMAC (via TFTP), and SPI flash - as documented in SPRS605C Section 4.4. Boot mode is selected via GPIO strap pins at reset, and the RBL validates image integrity before transferring control to user code in DDR2 or L2 RAM.
TMS320DM6467TCUTD1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- TMS320DM646x, DaVinci™
- Package/Case:
- 529-BFBGA, FCBGA
- Packaging:
- Tray
- Product Status:
- Active
- Type:
- Digital Media System-on-Chip (DMSoC)
- Interface:
- EBI/EMI, Ethernet, HPI, I2C, McASP, PCI, SPI, UART, USB
- Clock Rate:
- 1GHz DSP, 500MHz ARM®
- Non-Volatile Memory:
- ROM (8kB)
- On-Chip RAM:
- 248kB
- Voltage - I/O:
- 1.8V, 3.3V
- Voltage - Core:
- 1.30V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 529-FCBGA (19x19)
TMS320DM6467TCUTD1 FAQ
1.How can I place an order for TMS320DM6467TCUTD1 through Aetrix?
Please submit a Request for Quotation (RFQ) for TMS320DM6467TCUTD1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TMS320DM6467TCUTD1 reliable?
The price and inventory of TMS320DM6467TCUTD1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TMS320DM6467TCUTD1 is usually 5 days.
3.What payment methods are accepted for TMS320DM6467TCUTD1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TMS320DM6467TCUTD1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TMS320DM6467TCUTD1?
TMS320DM6467TCUTD1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TMS320DM6467TCUTD1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TMS320DM6467TCUTD1?
For technical support, including TMS320DM6467TCUTD1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TMS320DM6467TCUTD1 requirements.
6.How does Aetrix verify that TMS320DM6467TCUTD1 is sourced from the original manufacturer or authorized distributors?
All TMS320DM6467TCUTD1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TMS320DM6467TCUTD1 meets industry standards.
7.What is the process for return or replacement of TMS320DM6467TCUTD1?
All TMS320DM6467TCUTD1 units undergo pre-shipment inspection (PSI). If there is an issue with TMS320DM6467TCUTD1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TMS320DM6467TCUTD1 part is unused and in its original packaging.
Return procedure for TMS320DM6467TCUTD1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TMS320DM6467TCUTD1 Tags
-
TMS320C5535AZAY10
Texas Instruments
-
TMS320VC5501PGF300
Texas Instruments
-
ADSP-BF592KCPZ
Analog Devices Inc.
-
ADAU1463WBCPZ150
Analog Devices Inc.
-
TMS320VC5402PGE100
Texas Instruments
-
ADAU1701JSTZ-RL
Analog Devices Inc.
-
ADAU1701JSTZ
Analog Devices Inc.
-
TMS320VC5502PGF300
Texas Instruments
-
ADAU1462WBCPZ300RL
Analog Devices Inc.
-
ADAU1452KCPZRL
Analog Devices Inc.
-
ADAU1452WBCPZ-RL
Analog Devices Inc.
-
TMS320C6747DZKB3
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
