Texas Instruments TMS320DM8168CCYGH
- Part No.:
- TMS320DM8168CCYGH
- Manufacturer:
- Texas Instruments
- Category:
- DSP (Digital Signal Processors)
- Package:
- 1031-BFBGA, FCBGA
- Datasheet:
-
TMS320DM8168CCYGH.pdf
- Description:
- IC DGTL MEDIA PROCESSR 1031FCBGA
- Quantity:
- Payment:

- Shipping:

Inventory:4,006
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Product details
Overview
TMS320DM8168CCYGH from Texas Instruments is a high-performance DaVinci digital media processor integrating an ARM Cortex-A8 RISC CPU (up to 1.2 GHz), a C674x floating-point DSP core (up to 1 GHz), three HDVICP2 video coprocessors, SGX530 3D graphics engine, and dual DDR2/DDR3 memory interfaces - deployed in HD video security systems, media servers, and digital signage for real-time 1080p60 encode/decode/transcode.
For engineers reviewing the TMS320DM8168CCYGH datasheet, TMS320DM8168CCYGH pinout, TMS320DM8168CCYGH application, or TMS320DM8168CCYGH equivalent, key selection criteria include ARM+DSP heterogeneous compute capability, triple HDVICP2 acceleration, HDMI 1.3 transmitter support, 256KB L2 cache per core, and FCBGA-1031 package compatibility with industrial thermal and layout constraints.
Technical Context
The TMS320DM8168CCYGH implements a tightly coupled heterogeneous architecture: the ARM Cortex-A8 handles OS, control, and GUI via NEON-enhanced integer/FPU execution (32KB I-cache, 32KB D-cache, 256KB L2 cache), while the C674x DSP executes signal-intensive video algorithms with IEEE-754 SP/DP floating-point support (up to 8000 MIPS / 6000 MFLOPS) and dedicated VLIW functional units.
Video processing is offloaded to three independent HDVICP2 engines supporting concurrent H.264/MPEG-2/VC-1 encode/decode at 1080p60, coordinated by a programmable Media Controller and HDVPSS subsystem featuring dual 165-MHz HD capture/display channels, HDMI 1.3 transmitter with HDCP, and SD/HD analog output mixing - all mapped through a System MMU for unified virtual addressing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | ARM Cortex-A8 + C674x VLIW DSP - enables parallel OS control (ARM) and real-time video algorithm execution (DSP) without software co-scheduling overhead |
| CPU Frequency | Up to 1.20 GHz - delivers 930–1200 MHz operation depending on speed grade, enabling Linux RTOS boot and GUI rendering within <500 ms |
| DSP Frequency | Up to 1.00 GHz - supports four SP adds/cycle and two DP adds every two cycles for sustained 6000 MFLOPS video filtering |
| HDVICP2 Engines | Three independent coprocessors - each capable of full 1080p60 H.264 decode or encode, enabling simultaneous multi-stream transcoding (e.g., 2×1080p→4×720p) |
| Graphics Engine | SGX530 (30 MTri/s) - only on DM8168 - accelerates OpenGL ES 2.0 UI rendering and overlay composition for digital signage overlays |
| Memory Interface | Dual 32-bit DDR2/DDR3 - supports DDR2-800 and DDR3-1600 up to 2GB total, with DMM-based tiling/mirroring for efficient interlaced frame buffer access |
| Video I/O | Two 165-MHz HD capture + two 165-MHz HD display channels - allows simultaneous HD input (e.g., camera feed) and HDMI output (e.g., monitor) with zero-copy DMA |
| Package | FCBGA-1031 (25 mm × 25 mm, 0.65-mm pitch) - uses Via Channel technology for 2-layer PCB routing and reduced via count vs. standard BGA |
Pinout & Package
Package: FCBGA-1031 (25.0 mm × 25.0 mm, 0.65-mm pitch) with Via Channel technology enabling 0.8-mm PCB feature sizes and two-signal-layer routing efficiency.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| DEV_CLKIN | Reference Clock Input | 1.8-V tolerant input for system oscillator (19.2–40 MHz); required for PLL lock and clock domain initialization |
| DDR2/DDR3_DQ[31:0] | Data Bus (x2 interfaces) | Two independent 32-bit bidirectional data buses - supports interleaved access across DDR2 and DDR3 channels for >3.2 GB/s aggregate bandwidth |
| HDMI_TX_CLK | HDMI Pixel Clock Output | 165-MHz LVDS-compatible clock driving HDMI 1.3 transmitter; synchronized to HDVPSS display pipeline timing |
| HDVICP2_IRQ[2:0] | Coprocessor Interrupt Output | Three dedicated IRQ lines - one per HDVICP2 engine, enabling low-latency interrupt-driven completion signaling to ARM/DSP |
| GPMC_A[23:0] | Asynchronous Address Bus | 24-bit multiplexed address/data bus - supports glueless NAND/NOR/SRAM interfacing with BCH/Hamming ECC via ELM |
Key Features
| Feature | Design Value |
|---|---|
| Triple HDVICP2 Acceleration | Enables concurrent 1080p60 encode + decode + transcode - eliminating need for external ASICs in video infrastructure edge nodes |
| System MMU Mapping | Translates C674x DSP and EMDA TCB memory accesses to system addresses - allowing zero-copy buffers shared between ARM, DSP, and HDVICP2 without software synchronization |
| HDVPSS Dual Capture/Display | Supports split 8-bit SD capture per channel and simultaneous HD analog + HDMI digital output - critical for hybrid surveillance DVRs with legacy CVBS and modern display outputs |
| PCIe 2.0 x2 Root Complex | Provides 5.0 GT/s link to FPGA co-processors or NVMe storage - enabling offload of AI inference or high-throughput metadata analysis |
| SmartReflex Level 2 Power Management | Dynamically scales voltage/frequency per core domain (ARM, DSP, HDVICP2, HDVPSS) - reducing active power by up to 35% during partial-load video analytics |
Applications
| HD Video Security DVR | Media Server Transcoder |
|---|---|
Use Scenario: Multi-channel IP camera recording with real-time motion detection, facial recognition, and remote playback. IC Role / Device Role / Timing Role: TMS320DM8168CCYGH acts as the central media processing unit - ARM runs Linux and web server, DSP handles motion analytics, HDVICP2 engines compress 4×1080p streams simultaneously. Use Value: Triple HDVICP2 enables 4×1080p@30fps H.264 encoding with <50 ms end-to-end latency, eliminating frame drops during burst motion events. | Use Scenario: Cloud-edge media server converting broadcast MPEG-2 TS to adaptive HTTP streaming (HLS/DASH) for mobile delivery. IC Role / Device Role / Timing Role: TMS320DM8168CCYGH serves as hardware-accelerated transcoder - ARM orchestrates stream ingestion, HDVICP2 engines perform decode+encode+transrate, HDVPSS resizes/resamples frames. Use Value: Concurrent decode (MPEG-2) + encode (H.264) + transrate (bitrate ladder) on single chip reduces BOM cost by $12 vs. dual-ASIC solution while cutting power by 40%. |
| Digital Signage Player | Video Conferencing Endpoint |
Use Scenario: 4K-resolution retail display showing dynamic ads, weather, and live social feeds with touch interaction. IC Role / Device Role / Timing Role: TMS320DM8168CCYGH functions as multimedia SoC - ARM executes Qt-based GUI, SGX530 renders OpenGL ES 2.0 overlays, HDVPSS composites video layers onto HDMI output. Use Value: SGX530's 30 MTri/s geometry throughput enables smooth 60 fps UI animation with 3D transitions, even with 4×HD video backgrounds. | Use Scenario: Compact room system capturing dual-camera feeds (front + whiteboard), performing speaker tracking, and transmitting encrypted 1080p30 video. IC Role / Device Role / Timing Role: TMS320DM8168CCYGH operates as endpoint SoC - ARM manages WebRTC stack and encryption, DSP runs acoustic echo cancellation, HDVICP2 encodes dual streams. Use Value: Dual HD capture channels + triple HDVICP2 allow simultaneous encode of primary speaker (1080p) and whiteboard (720p) at <100 ms round-trip latency. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital media processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TMS320DM8167CYG | Same ARM/DSP/HDVPSS/PCIe/USB/Ethernet peripherals but lacks SGX530 graphics engine and has only two HDVICP2 engines | Suitable for headless video infrastructure where GUI rendering is handled externally; not viable for integrated digital signage with 3D UI | Select when 3D graphics and third HDVICP2 are unnecessary - reduces cost and thermal load |
| i.MX6Q | ARM Cortex-A9 quad-core (1 GHz), no dedicated DSP, Vivante GC2000 GPU (200 MHz), single video encoder (1080p30), no HDVICP2 | Targeted at general-purpose embedded UI with light video playback; cannot match TMS320DM8168CCYGH's real-time multi-stream encode/decode throughput | Choose for cost-sensitive applications requiring Android/Linux GUI but no heavy video transcoding |
Compared with TMS320DM8167CYG, TMS320DM8168CCYGH adds SGX530 graphics and a third HDVICP2 - enabling standalone digital signage and higher-density video infrastructure. Against i.MX6Q, it delivers 3× higher video encode throughput and hardware-accelerated DSP math, at the cost of higher power and toolchain complexity.
Availability
TMS320DM8168CCYGH is available at Aetrix Electronics and suitable for HD video security DVRs, media server transcoders, and digital signage players requiring stable component supply across extended product lifecycles and industrial temperature ranges.
Supply support for TMS320DM8168CCYGH includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, delivering analog and embedded processing solutions for industrial, automotive, and communications markets since 1930.
The TMS320DM8168CCYGH belongs to TI's DaVinci digital media processor family - engineered specifically for high-definition video infrastructure applications demanding heterogeneous ARM+DSP compute, hardware-accelerated video codecs, and rich peripheral integration in a single SoC.
FAQ
What is the maximum operating frequency of the ARM Cortex-A8 core in the TMS320DM8168CCYGH?
The TMS320DM8168CCYGH ARM Cortex-A8 core operates at up to 1.20 GHz, with speed grades supporting 930 MHz, 1.10 GHz, and 1.20 GHz configurations. This frequency enables fast Linux kernel boot, real-time scheduling of video pipelines, and responsive GUI rendering using the integrated SGX530 graphics engine - all verified in TI's SPRS614F datasheet revision March 2015.
Does the TMS320DM8168CCYGH support HDMI 2.0 or only HDMI 1.3?
The TMS320DM8168CCYGH integrates an HDMI 1.3 transmitter with PHY supporting up to 165-MHz pixel clock - sufficient for 1080p60 RGB/YCbCr 4:4:4 but not HDMI 2.0 features like 4K60 or HDR. It does not support HDMI 2.0 protocol extensions, HDCP 2.2, or enhanced audio return channel (eARC). This is explicitly stated in Section 1.1 and Figure 1-1 of the SPRS614F datasheet.
How many HDVICP2 video coprocessors are implemented in the TMS320DM8168CCYGH?
The TMS320DM8168CCYGH contains three fully independent HDVICP2 video coprocessors - confirmed in Table 3-1 (Device Comparison) and Section 1.1 of the SPRS614F datasheet. Each supports full 1080p60 H.264/MPEG-2/VC-1 encode or decode, enabling true concurrent multi-stream processing unmatched by dual-HDVICP2 variants like the DM8167.
Is the SGX530 graphics engine present in all TMS320DM8168CCYGH units?
Yes, the SGX530 3D graphics engine is present in every TMS320DM8168CCYGH device - explicitly designated as "available only on the TMS320DM8168 devices" in Figure 1-1 and Section 3.8 of the SPRS614F datasheet. It delivers 30 MTriangles/s and supports OpenGL ES 1.1/2.0, OpenVG 1.1, and Direct3D Mobile for rich UI acceleration in digital signage and video conferencing endpoints.
What package type and pin count does the TMS320DM8168CCYGH use?
The TMS320DM8168CCYGH uses a 1031-pin FCBGA package measuring 25.0 mm × 25.0 mm with 0.65-mm ball pitch - documented in the Device Information table on page 4 of SPRS614F. It employs Via Channel technology to enable 0.8-mm PCB feature sizes and efficient two-layer routing, distinguishing it from standard BGA packages.
TMS320DM8168CCYGH Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- DM81x Video SOC, DaVinci™
- Package/Case:
- 1031-BFBGA, FCBGA
- Packaging:
- Tray
- Product Status:
- Active
- Type:
- Digital Media System-on-Chip (DMSoC)
- Interface:
- EBI/EMI, Ethernet, I2C, McASP, McBSP, PCI, Serial ATA, SD/SDIO, SPI, UART, USB
- Clock Rate:
- 800MHz DSP, 1.0GHz ARM®
- Non-Volatile Memory:
- ROM (48kB)
- On-Chip RAM:
- 1.5MB
- Voltage - I/O:
- 1.5V, 1.8V, 3.3V
- Voltage - Core:
- 1.00V
- Operating Temperature:
- 0°C ~ 95°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 1031-FCBGA (25x25)
TMS320DM8168CCYGH FAQ
1.How can I place an order for TMS320DM8168CCYGH through Aetrix?
Please submit a Request for Quotation (RFQ) for TMS320DM8168CCYGH on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TMS320DM8168CCYGH reliable?
The price and inventory of TMS320DM8168CCYGH are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TMS320DM8168CCYGH is usually 5 days.
3.What payment methods are accepted for TMS320DM8168CCYGH?
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4.How is shipping managed for TMS320DM8168CCYGH?
TMS320DM8168CCYGH orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TMS320DM8168CCYGH order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TMS320DM8168CCYGH?
For technical support, including TMS320DM8168CCYGH datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TMS320DM8168CCYGH requirements.
6.How does Aetrix verify that TMS320DM8168CCYGH is sourced from the original manufacturer or authorized distributors?
All TMS320DM8168CCYGH products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TMS320DM8168CCYGH meets industry standards.
7.What is the process for return or replacement of TMS320DM8168CCYGH?
All TMS320DM8168CCYGH units undergo pre-shipment inspection (PSI). If there is an issue with TMS320DM8168CCYGH, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TMS320DM8168CCYGH part is unused and in its original packaging.
Return procedure for TMS320DM8168CCYGH:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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