Texas Instruments TMS320F28032PAGT
- Part No.:
- TMS320F28032PAGT
- Manufacturer:
- Texas Instruments
- Category:
- Microcontrollers
- Package:
- 64-TQFP
- Datasheet:
-
TMS320F28032PAGT.pdf
- Description:
- IC MCU 32BIT 64KB FLASH 64TQFP
- Quantity:
- Payment:

- Shipping:

Inventory:632
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TMS320F28032PAGT from Texas Instruments is a 60-MHz C28x-core real-time microcontroller with integrated Control Law Accelerator (CLA), 32 KB flash, 10 KB SARAM, 12-bit 4.6 MSPS ADC, 8 ePWM channels, and 64-pin TQFP package. It targets motor control, digital power conversion, and EV charging systems requiring deterministic low-latency control.
For engineers reviewing the TMS320F28032PAGT datasheet, TMS320F28032PAGT pinout, TMS320F28032PAGT application, or TMS320F28032PAGT equivalent, key selection criteria include CLA offload capability, HRPWM dual-edge modulation support, analog comparator routing to PWM, ADC sample-and-hold timing, and TQFP-64 thermal performance in industrial temperature range (–40°C to 105°C).
Technical Context
The TMS320F28032PAGT implements a Harvard-architecture C28x CPU with atomic instructions and fast interrupt response, paired with a dedicated 32-bit floating-point CLA that executes control loops independently of the main CPU. Its memory map includes secure flash, boot ROM, and CLA-accessible peripheral registers.
Peripheral integration centers on real-time actuation: ePWM modules support high-resolution edge control and synchronization; ADC features dual sample-and-hold and ratio-metric reference inputs; comparators route outputs directly to PWM trip zones for hardware fault response without CPU intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | C28x 32-bit fixed-point, 60 MHz (16.67 ns cycle time), Harvard bus, unified memory model |
| Control Law Accelerator | Dedicated 32-bit floating-point accelerator executing independent code; present in TMS320F28032 but not F28030/F28031 |
| Flash Memory | 32 KB × 16-bit, secured via 128-bit key; supports in-field updates with ECC and erase/write protection |
| ADC | 12-bit, 4.6 MSPS, 16-channel with dual sample-and-hold; conversion time 216.67 ns, VREFHI/VREFLO ratio-metric reference |
| ePWM Channels | 8 independent channels with high-resolution extension (HRPWM) enabling dual-edge modulation for frequency control |
| Package & Temp | 64-pin TQFP (PAG), 10.0 mm × 10.0 mm; rated for –40°C to 105°C (T-grade) |
| I/O Count | 33 GPIO pins (multiplexed), 6 AIO pins; all GPIO support input filtering and configurable pull-up/pull-down |
Pinout & Package
64-pin Thin Quad Flatpack (TQFP), body size 10.0 mm × 10.0 mm, lead pitch 0.5 mm, RoHS-compliant, moisture sensitivity level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VDDA, VDDIO | Power supply rails | VDD = 3.3 V core/digital; VDDA = 3.3 V analog; VDDIO = 3.3 V I/O; internal regulator enables single-rail operation |
| VSS, VSSA, VREFLO | GND and reference return | VSS = digital ground; VSSA = analog ground; VREFLO tied internally to VSSA on PAG package |
| X1, X2 | Clock oscillator terminals | Support external crystal (4–20 MHz) or external clock source; PLL generates system clock up to 60 MHz |
| GPIO0–GPIO33 | General-purpose I/O | Configurable as digital I/O, peripheral multiplex (ePWM, eCAP, eQEP, SPI, SCI, I2C, LIN, eCAN), with input filtering and per-pin pull control |
| ADCINA0–ADCINA7, ADCINB0–ADCINB7 | Analog input channels | 16 total ADC inputs; grouped into two banks (A/B); support simultaneous sampling via dual sample-and-hold |
| COMP1A–COMP3B | Comparator inputs | 3 analog comparators with internal 10-bit DAC references; outputs routable to ePWM trip-zones for hardware protection |
| TCK, TMS, TDI, TDO, TRST | JTAG debug interface | IEEE 1149.1 compliant; TRST requires external 2.2-kΩ pulldown; supports real-time emulation and boundary scan |
Key Features
| Feature | Design Value |
|---|---|
| Programmable Control Law Accelerator (CLA) | Offloads time-critical control loops (e.g., field-oriented control) from C28x CPU, reducing latency and freeing CPU for communication and supervision |
| High-Resolution PWM (HRPWM) | Enables sub-nanosecond duty-cycle resolution and dual-edge modulation for precise frequency/phase control in resonant converters and motor drives |
| Analog Comparator + PWM Integration | Comparator outputs directly trigger ePWM trip-zones, enabling <100 ns fault response without software intervention or CPU overhead |
| On-chip Voltage Regulator | Generates internal 1.8-V supply from 3.3-V input, eliminating need for external LDO and simplifying power sequencing |
| Code Security Module | 128-bit encryption key locks flash/SARAM/OTP; prevents firmware reverse engineering and unauthorized reprogramming |
Applications
| Motor Drive Control | Digital Power Conversion |
|---|---|
Use Scenario: Closed-loop field-oriented control (FOC) of 3-phase BLDC/PMSM motors in HVAC compressors and industrial pumps. IC Role / Device Role / Timing Role: Real-time execution of current/voltage loop control, space-vector PWM generation, and encoder-based position feedback processing. Use Value: CLA accelerates FOC math; HRPWM enables >100 kHz switching with precise dead-time control; ADC simultaneous sampling captures phase currents with <217 ns latency. | Use Scenario: Bidirectional DC/DC conversion in EV on-board chargers (OBC) and energy storage PCS systems. IC Role / Device Role / Timing Role: Digital controller for phase-shifted full-bridge or LLC resonant topologies, managing voltage/current regulation and soft-switching timing. Use Value: Dual-edge HRPWM adjusts frequency and duty cycle independently; comparator-triggered trip zones protect against overcurrent within hardware; 4.6 MSPS ADC samples isolated current sensors at 10 kHz control rate. |
| EV Charging Station | Solar Inverter Control |
Use Scenario: AC-input and DC-output power stage control in Level 2 AC charging stations and DC fast-charging modules. IC Role / Device Role / Timing Role: Primary controller for grid-synchronization (PLL), active/reactive power regulation, and thermal management of SiC MOSFET gate drivers. Use Value: eCAN and LIN interfaces communicate with BMS and vehicle; 33 GPIOs support isolation monitoring and contactor control; 105°C rating ensures reliability in outdoor enclosures. | Use Scenario: MPPT and grid-synchronization in string inverters and solar power optimizers. IC Role / Device Role / Timing Role: High-speed sampling of PV voltage/current, real-time perturb-and-observe algorithm, and IEEE 1547-compliant anti-islanding detection. Use Value: 12-bit ADC with ratio-metric reference rejects supply variation; CLA computes MPPT in parallel with grid sync; eQEP module reads encoder feedback from tracking mounts. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar real-time control applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TMS320F28033PAGT | Includes CLA and 64 KB flash; adds 2 HRCAP modules and 2 eQEP modules vs. TMS320F28032PAGT | Required for applications needing quadrature encoder position feedback and high-resolution capture of fast transients | Select when encoder-based motion control or multi-sensor timing alignment is needed beyond TMS320F28032PAGT capability |
| TMS320F28034PAGT | Same flash (32 KB) and CLA as TMS320F28032PAGT; adds 1 eQEP and 2 HRCAP modules | Suitable for systems requiring one encoder interface plus high-resolution event capture without full F28033 feature set | Choose for cost-sensitive designs needing incremental upgrade over TMS320F28032PAGT with minimal footprint change |
Compared with TMS320F28032PAGT, TMS320F28033PAGT provides expanded motion control peripherals and memory for complex algorithms, while TMS320F28034PAGT offers balanced enhancement in capture and position sensing-both retain identical 64-pin TQFP packaging and industrial temperature rating.
Availability
TMS320F28032PAGT is available at Aetrix Electronics and suitable for motor drive control, digital power conversion, and EV charging station power modules requiring stable component supply across extended industrial temperature ranges.
Supply support for TMS320F28032PAGT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company delivering analog and embedded processing solutions, with leadership in real-time control, power management, and signal chain technologies.
The TMS320F2803x product line delivers entry-performance C2000™ real-time MCUs optimized for cost-sensitive industrial motor drives, solar inverters, and digital power systems-emphasizing analog integration, CLA acceleration, and low-pin-count packaging.
FAQ
What is the maximum operating frequency of the TMS320F28032PAGT CPU core?
The TMS320F28032PAGT CPU core operates at a maximum frequency of 60 MHz, corresponding to a 16.67 ns instruction cycle time. This timing is achieved using the on-chip PLL driven by either an external crystal (X1/X2) or external clock input (XCLKIN), with internal voltage regulation supporting stable 3.3-V operation. The TMS320F28032PAGT maintains this speed across its full industrial temperature range (–40°C to 105°C).
Does the TMS320F28032PAGT include a Control Law Accelerator (CLA)?
Yes, the TMS320F28032PAGT includes a dedicated 32-bit floating-point Control Law Accelerator (CLA) that executes control code independently of the main C28x CPU. This feature is confirmed in the device comparison table and distinguishes TMS320F28032PAGT from earlier F28030/F28031 variants. The CLA reduces CPU load during high-frequency control loops such as FOC or resonant converter regulation in the TMS320F28032PAGT.
What ADC performance specifications apply to the TMS320F28032PAGT?
The TMS320F28032PAGT integrates a 12-bit analog-to-digital converter with 4.6 MSPS throughput, 16 input channels, and dual sample-and-hold capability. Its conversion time is 216.67 ns, and it supports ratio-metric referencing using VREFHI/VREFLO. These parameters are validated in the device comparison table and electrical characteristics section of the official datasheet for the TMS320F28032PAGT.
Which package and temperature grade does the TMS320F28032PAGT use?
The TMS320F28032PAGT uses a 64-pin Thin Quad Flatpack (TQFP) package designated "PAG", with body dimensions of 10.0 mm × 10.0 mm. It is rated for the industrial temperature range of –40°C to 105°C (T-grade), as specified in the device ordering information and temperature options table for the TMS320F28032PAGT.
How many ePWM channels does the TMS320F28032PAGT support, and what resolution features are included?
The TMS320F28032PAGT supports 8 ePWM channels, each enhanced with High-Resolution PWM (HRPWM) capability enabling sub-nanosecond duty-cycle adjustment and independent control of both rising and falling edges. This allows precise frequency modulation in resonant topologies and fine-grained dead-time management-key features documented in the peripheral description and device comparison for the TMS320F28032PAGT.
TMS320F28032PAGT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 64-TQFP
- Series:
- C2000™ C28x Piccolo™
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- C28x
- Core Size:
- 32-Bit Single-Core
- Speed:
- 60MHz
- Connectivity:
- CANbus, I2C, LINbus, SCI, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, POR, PWM, WDT
- Number of I/O:
- 33
- Program Memory Size:
- 64KB (32K x 16)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 10K x 16
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 1.995V
- Data Converters:
- A/D 14x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
TMS320F28032PAGT FAQ
1.How can I place an order for TMS320F28032PAGT through Aetrix?
Please submit a Request for Quotation (RFQ) for TMS320F28032PAGT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TMS320F28032PAGT reliable?
The price and inventory of TMS320F28032PAGT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TMS320F28032PAGT is usually 5 days.
3.What payment methods are accepted for TMS320F28032PAGT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TMS320F28032PAGT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TMS320F28032PAGT?
TMS320F28032PAGT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TMS320F28032PAGT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TMS320F28032PAGT?
For technical support, including TMS320F28032PAGT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TMS320F28032PAGT requirements.
6.How does Aetrix verify that TMS320F28032PAGT is sourced from the original manufacturer or authorized distributors?
All TMS320F28032PAGT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TMS320F28032PAGT meets industry standards.
7.What is the process for return or replacement of TMS320F28032PAGT?
All TMS320F28032PAGT units undergo pre-shipment inspection (PSI). If there is an issue with TMS320F28032PAGT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TMS320F28032PAGT part is unused and in its original packaging.
Return procedure for TMS320F28032PAGT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TMS320F28032PAGT Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

