Texas Instruments TMS55161-70ADGH

Overview

TMS55161-70ADGH from Texas Instruments is a 262,144 × 16-bit dual-port video RAM (VRAM) with DRAM + serial-access memory (SAM) architecture, supporting simultaneous asynchronous access from both ports, 70 ns DRAM row-access time, EDO mode for extended data output, and 4-column block-write capability - used in high-bandwidth graphics subsystems for real-time pixel rendering and CRT display buffering.

For engineers reviewing the TMS55161-70ADGH datasheet, TMS55161-70ADGH pinout, TMS55161-70ADGH application, or TMS55161-70ADGH equivalent, key selection criteria include its 5.0-V ±10% supply, TTL-compatible I/O, split-register-transfer support for uninterrupted 55-MHz serial streams, and compatibility with TI's graphics processor family.

Technical Context

The TMS55161-70ADGH integrates a 512 × 512 DRAM array (262,144 words × 16 bits) with a 256-word × 16-bit static serial register (SAM), enabling concurrent DRAM random access and SAM serial streaming. Its enhanced page mode reduces latency during column-addressed reads within an active row.

This device implements EDO functionality: DRAM outputs remain valid after CASx goes high while RAS and TRG are low, shortening system cycle time. It supports CBR and hidden refresh modes, with full- and split-register-transfer operations allowing real-time DRAM-to-SAM data movement without interrupting serial output.

Key Specifications

Pinout & Package

Package: 64-pin SOIC (gull-wing, DGH suffix), surface-mount compatible, with 32 VSS/VCC pins distributed for noise suppression and thermal management.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-port video RAM applications.

Compared with TMS55160-70ADGH, the TMS55161-70ADGH delivers faster system-level bandwidth via EDO; compared with TMS55171-70ADGH, it trades 8-column fill capability for tighter layout compatibility with legacy 4-column graphics controller designs.

Availability

TMS55161-70ADGH is available at Aetrix Electronics and suitable for graphics controller framebuffer, real-time video overlay engine, high-speed CRT display buffer, and industrial vector graphics terminal applications requiring stable component supply across long-lifecycle embedded programs.

Supply support for TMS55161-70ADGH includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a U.S.-based semiconductor innovator founded in 1930, specializing in analog, embedded processing, and digital signal technologies for industrial, automotive, and computing markets.

The TMS551xx VRAM product line was designed specifically for high-bandwidth graphics subsystems requiring concurrent random and serial memory access - targeting compatibility with TI's TMS340xx graphics processors and CRT display timing requirements.

FAQ

What is the maximum serial data rate supported by the TMS55161-70ADGH?

The TMS55161-70ADGH supports uninterrupted serial-data streams up to 55 MHz, enabled by its static serial-access memory (SAM) and TTL-compatible SQ0–SQ15 outputs. This rate is achievable under specified operating conditions (5.0 V ±0.5 V, 0°C to 70°C) and requires proper SC timing and SE assertion. The QSF pin provides real-time half-register status for external synchronization, making the TMS55161-70ADGH suitable for CRT pixel-clock-critical applications.

Does the TMS55161-70ADGH support extended data output (EDO) mode?

Yes, the TMS55161-70ADGH supports EDO mode, a key differentiator from the TMS55160-70ADGH. In EDO mode, DRAM outputs remain valid after CASx returns high while RAS and TRG are low - reducing minimum DRAM cycle time to 30 ns. This feature is active in both standard and enhanced page-mode reads and directly improves sustained bandwidth in graphics pipelines that perform burst reads, such as those found in TI TMS340xx-based controllers.

How does the split-register-transfer function work in the TMS55161-70ADGH?

The TMS55161-70ADGH divides its 256-word SAM into high and low halves. During split-register-transfer, one half streams serial data out via SQ0–SQ15 while the other half concurrently loads new data from the DRAM - enabled by asserting TRG low and DSF high on RAS fall. This decouples display output from memory update, eliminating gaps in serial streams. The QSF pin indicates which half is active, allowing external logic to align shifts or manage double-buffered timing without CPU intervention.

What is the purpose of the DSF pin on the TMS55161-70ADGH?

The DSF (Special-Function Select) pin on the TMS55161-70ADGH determines operational mode based on its state at RAS and CASx falling edges. When latched low on RAS and high on CASx, it enables 4-column block-write; high on both edges configures split-register-transfer; high on RAS and low on CASx triggers load-write-mask-register (LMR) cycles. DSF thus serves as a mode-select input rather than a fixed-function control, allowing dynamic configuration of advanced VRAM features without additional address decoding logic.

Is the TMS55161-70ADGH pin-compatible with other devices in the TMS551xx family?

Yes, the TMS55161-70ADGH shares identical 64-pin DGH package, pinout, and electrical interface with TMS55160-70ADGH, TMS55170-70ADGH, and TMS55171-70ADGH. All variants use the same A0–A8, RAS, CASL/CASU, WE, TRG, DQ0–DQ15, SC, SE, SQ0–SQ15, QSF, DSF, VCC, VSS, and NC/GND assignments. Functional differences (e.g., EDO, 4- vs. 8-column block-write) are implemented internally and do not affect PCB layout - enabling drop-in replacement within the same speed grade and package.