My Inquiry
My Account
Texas Instruments TMUX136RSER
- Part No.:
- TMUX136RSER
- Manufacturer:
- Texas Instruments
- Package:
- 10-UFQFN
- Datasheet:
-
TMUX136RSER.pdf
- Description:
- IC SWITCH SPDT X 2 9.5OHM 10UQFN
- Quantity:
- Payment:
- Shipping:
Inventory:45,822
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TMUX136RSER from Texas Instruments is a 6-GHz, 2-channel, 2:1 analog switch optimized for high-speed digital protocols including I3C and MIPI. It features 5.7 Ω typical on-resistance, 1.6 pF typical on-capacitance, 6.1 GHz –3 dB bandwidth, and operates from 2.3 V to 4.8 V supply. It enables signal routing in smartphone baseband subsystems with power-off isolation and 1.8-V compatible control inputs.
For engineers reviewing the TMUX136RSER datasheet, TMUX136RSER pinout, TMUX136RSER application, or TMUX136RSER equivalent, key selection criteria include bandwidth preservation at >3 Gbps data rates, low jitter contribution (≤8.4 ps peak-to-peak), flow-through UQFN layout compatibility, and IOFF protection for system-level power sequencing integrity.
Technical Context
The TMUX136RSER implements a bidirectional, dual SPDT architecture with independent A/B port switching controlled by SEL and enabled globally by active-low EN. Its charge-pump-assisted switch core maintains flat RON across 0–3.6 V I/O swing and supports both single-ended and differential signaling without polarity constraints.
It integrates internal 6-MΩ pull-down resistors on SEL and EN pins, enabling default A-port selection and automatic enable-on-power-up behavior. The device enters true high-impedance mode when EN = high or VCC = 0 V, delivering ≤±10 µA power-off leakage and ≥–34 dB OFF isolation at 240 MHz.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 2.3 V to 4.8 V - supports direct interface with 2.5 V/3.3 V/4.5 V rails and battery-backed systems |
| –3 dB Bandwidth | 6.1 GHz - preserves edge integrity for I3C (up to 12.5 MHz bus) and 4.5 Gbps serial links |
| RON (typ) | 5.7 Ω - minimizes insertion loss and voltage drop in 50-Ω impedance-matched paths |
| CON (typ) | 1.6 pF - limits capacitive loading on high-speed buses, critical for maintaining eye opening |
| IOFF Leakage | ±10 µA at VCC = 0 V - ensures signal integrity during hot-swap or partial power-down sequences |
| Propagation Delay | 100 ps - enables sub-nanosecond timing alignment in synchronous multiplexing applications |
| ESD Rating | ±5 kV HBM - meets IEC 61000-4-2 Level 4 requirements for handheld end-equipment |
Pinout & Package
TMUX136RSER is housed in a 10-pin UQFN package (1.5 mm × 2.0 mm, 0.5-mm pitch) with wettable flanks and RoHS-compliant NiPdAu lead finish. The flow-through pinout places all I/O signals on opposing edges to minimize trace stubs and crosstalk in dense PCB layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 A1 | I/O signal path A1 | First channel input/output for Port A; bidirectional, supports differential pair routing |
| 2 A2 | I/O signal path A2 | Second channel input/output for Port A; paired with A1 for full-duplex I3C SCL/SDA switching |
| 3 B1 | I/O signal path B1 | First channel input/output for Port B; used for alternate DDR module or sensor interface |
| 4 B2 | I/O signal path B2 | Second channel input/output for Port B; complements B1 for MIPI DSI/CSI lane expansion |
| 5 GND | Ground reference | Primary return path for analog and digital domains; must connect to solid ground plane |
| 6 EN | Active-low enable input | Global switch disable; logic high forces all COM/A/B paths into high-impedance state |
| 7 COM2 | Common output 2 | Second switched output node; connects to host controller's second differential lane |
| 8 COM1 | Common output 1 | First switched output node; routes to primary I3C master or MIPI host interface |
| 9 SEL | Channel select input | Logic low selects COM→A path; logic high selects COM→B path; 1.8-V compatible |
| 10 VCC | Positive supply | Power rail for internal charge pump and logic; requires local 0.1-µF bypass capacitor |
Key Features
| Feature | Design Value |
|---|---|
| Power-off isolation | IOFF ≤ ±10 µA at VCC = 0 V - prevents backfeeding and signal corruption during system suspend |
| Flow-through pinout | Inputs (A1/A2/B1/B2) on left, outputs (COM1/COM2) on right - eliminates layer transitions and vias in high-speed routing |
| I3C protocol support | Bandwidth >6 GHz + <2 pF capacitance - meets I3C SenseWire timing budget with ≤5.8 ps added jitter at 3 Gbps |
| 1.8-V logic compatibility | VIH = 1.3 V min, VIL = 0.6 V max - allows direct connection to 1.8-V GPIO without level shifters |
| Low dynamic power | ICC = 30 µA typical - extends battery life in always-on mobile sensor hubs and modem coexistence circuits |
Applications
| I3C Bus Multiplexing | MIPI DSI/CSI Lane Switching |
|---|---|
Use Scenario: Routing I3C communication between one master controller and two DDR memory modules in a compact smartphone SoC design. IC Role / Device Role / Timing Role: Dual-channel 2:1 switch providing time-shared access to shared I3C bus lines while preserving signal integrity up to 12.5 MHz clock rate. Use Value: Enables memory vendor flexibility without redesigning baseband PCB; maintains <5.8 ps jitter addition at 3 Gbps to meet I3C timing margins. | Use Scenario: Dynamically assigning MIPI display (DSI) and camera (CSI) lanes to alternate peripherals in tablet platforms with limited SoC pin count. IC Role / Device Role / Timing Role: High-bandwidth analog switch supporting bidirectional MIPI signals up to 4.5 Gbps per lane with minimal skew (<20 ps). Use Value: Reduces required SoC package I/O count by 4–6 pins; flow-through layout avoids impedance discontinuities that degrade MIPI eye diagrams. |
| Server Memory Interconnect | Portable Monitor Interface Aggregation |
Use Scenario: Sharing a single I3C controller across multiple DDR5 memory modules in edge-server DIMM modules with thermal/power constraints. IC Role / Device Role / Timing Role: Low-leakage, high-isolation switch enabling hot-plug detection and selective memory activation without bus contention. Use Value: IOFF protection prevents current leakage during module insertion/removal; –34 dB OFF isolation suppresses crosstalk between inactive channels. | Use Scenario: Consolidating USB-C Alt Mode DisplayPort and USB 3.2 Gen2 signals onto a single connector in ultra-thin portable monitors. IC Role / Device Role / Timing Role: Signal router managing DP++ and SuperSpeed USB lanes with simultaneous high-frequency operation and DC coupling capability. Use Value: 6.1 GHz bandwidth supports full DP 1.4a (8.1 Gbps) and USB 3.2 Gen2 (10 Gbps); 1.6 pF CON avoids excessive equalization overhead. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar analog switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TMUX1574RTER | 4-channel, 2:1 configuration; higher RON (7.5 Ω typ); same 6-GHz bandwidth and UQFN-16 package | Supports quad-lane I3C or dual MIPI CSI-2 streams; requires more PCB area and routing complexity | Select when expanding beyond dual-channel needs while retaining identical signal integrity specs |
| TS3USB30EIRWYR | Single 2:1 switch; 5-GHz bandwidth; 8.5 Ω RON; 2.5-pF CON; 10-pin UQFN but different pinout | Targeted at USB 2.0 and HDMI 1.4; lacks I3C-optimized low-jitter performance and power-off isolation | Choose only for cost-sensitive USB/HDMI applications where 6-GHz bandwidth and IOFF are not required |
Compared with TMUX136RSER, TMUX1574RTER offers channel scalability at the cost of layout density, while TS3USB30EIRWYR trades bandwidth and isolation for lower unit cost in legacy interface applications - neither provides drop-in replacement capability due to pinout and functional differences.
Availability
TMUX136RSER is available at Aetrix Electronics and suitable for smartphone baseband routing, I3C memory expansion, and MIPI display/camera switching requiring stable component supply across automotive-grade temperature ranges (–40°C to +125°C).
Supply support for TMUX136RSER includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and connectivity technologies with over 50 years of innovation in high-performance signal-path solutions.
The TMUX136RSER belongs to TI's high-speed analog switch product line, engineered specifically for next-generation mobile and server interfaces demanding GHz-range bandwidth, ultra-low capacitance, and robust power sequencing behavior.
FAQ
What is the maximum data rate supported by TMUX136RSER without violating signal integrity?
TMUX136RSER supports clean signal transmission up to 4.5 Gbps, as validated by eye diagram testing showing only 7.6 ps peak-to-peak jitter addition. Its 6.1 GHz –3 dB bandwidth exceeds the Nyquist frequency of 4.5 Gbps NRZ signals (2.25 GHz), ensuring minimal amplitude and phase distortion in I3C, MIPI DSI, and USB 3.2 Gen2 applications. The device's 1.6 pF CON and 5.7 Ω RON further preserve impedance matching and voltage swing.
Does TMUX136RSER require external pull-up or pull-down resistors on SEL and EN pins?
No, TMUX136RSER does not require external pull-up or pull-down resistors on SEL or EN. It integrates internal 6-MΩ pull-down resistors on both pins, enabling default A-port selection (SEL = low) and automatic enable-on-power-up (EN = low when VCC rises). This simplifies BOM and reduces layout area, especially in space-constrained mobile designs where TMUX136RSER is commonly deployed.
How does TMUX136RSER behave when VCC is disconnected during system operation?
When VCC is disconnected, TMUX136RSER enters power-off protection mode: all I/O pins (A1, A2, B1, B2, COM1, COM2) transition to high-impedance state with IOFF leakage ≤ ±10 µA. This prevents back-driving, signal corruption, or latch-up in partially powered systems - a critical feature for hot-swap memory modules and modular smartphone accessories where TMUX136RSER manages interconnect integrity.
Can TMUX136RSER be used for differential signaling such as MIPI or I3C?
Yes, TMUX136RSER is explicitly designed for differential signaling. Its bidirectional architecture, matched RON (ΔRON ≤ 0.1 Ω), low skew (<20 ps), and symmetric capacitance (<2 pF) ensure minimal common-mode noise and skew-induced jitter. TI application data confirms its use in MIPI DSI/CSI and I3C SenseWire implementations, where TMUX136RSER maintains eye opening and meets timing budgets up to 4.5 Gbps.
What PCB layout practices are essential to achieve specified 6.1 GHz bandwidth with TMUX136RSER?
To achieve the rated 6.1 GHz bandwidth, route TMUX136RSER's high-speed traces over continuous ground planes with no splits, limit trace length to ≤4 inches, avoid vias and 90° bends (use 45° or arcs), and place the 0.1-µF VCC bypass capacitor within 2 mm of the pin. TI recommends a 4-layer stack-up (signal/GND/power/signal) and prohibits routing near clocks or magnetics - practices validated in TMUX136RSER layout examples and eye-diagram test reports.
TMUX136RSER Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Switch Circuit:
- SPDT
- Multiplexer/Demultiplexer Circuit:
- 2:1
- Number of Circuits:
- 2
- On-State Resistance (Max):
- 9.5Ohm
- Channel-to-Channel Matching (ΔRon):
- 100mOhm
- Voltage - Supply, Single (V+):
- 2.3V ~ 4.8V
- Voltage - Supply, Dual (V±):
- -
- Switch Time (Ton, Toff) (Max):
- -
- -3db Bandwidth:
- 6.1GHz
- Charge Injection:
- -
- Channel Capacitance (CS(off), CD(off)):
- 1.6pF, 1.6pF
- Current - Leakage (IS(off)) (Max):
- 2µA
- Crosstalk:
- -37dB @ 240MHz
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-UQFN (2.0x1.5)
TMUX136RSER FAQ
1.How can I place an order for TMUX136RSER through Aetrix?
Please submit a Request for Quotation (RFQ) for TMUX136RSER on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TMUX136RSER reliable?
The price and inventory of TMUX136RSER are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TMUX136RSER is usually 5 days.
3.What payment methods are accepted for TMUX136RSER?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TMUX136RSER transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TMUX136RSER?
TMUX136RSER orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TMUX136RSER order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TMUX136RSER?
For technical support, including TMUX136RSER datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TMUX136RSER requirements.
6.How does Aetrix verify that TMUX136RSER is sourced from the original manufacturer or authorized distributors?
All TMUX136RSER products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TMUX136RSER meets industry standards.
7.What is the process for return or replacement of TMUX136RSER?
All TMUX136RSER units undergo pre-shipment inspection (PSI). If there is an issue with TMUX136RSER, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TMUX136RSER part is unused and in its original packaging.
Return procedure for TMUX136RSER:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TMUX136RSER Tags
-
SN74LVC1G3157DBVR
Texas Instruments
-
SN74LVC1G66DBVR
Texas Instruments
-
SN74LVC1G66DCKR
Texas Instruments
-
SN74LVC1G3157DSFR
Texas Instruments
-
1P1G3157QDCKRQ1
Texas Instruments
-
SN74LVC2G66DCUR
Texas Instruments
-
SN74LV4052APWR
Texas Instruments
-
74HC4051D,653
Nexperia USA Inc.
-
SN74LV4051APWR
Texas Instruments
-
CD74HC4052PWR
Texas Instruments
-
CD74HC4051PWR
Texas Instruments
-
TS5A3166DBVR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
