Texas Instruments TMX5700914APGEQQ1
- Part No.:
- TMX5700914APGEQQ1
- Manufacturer:
- Texas Instruments
- Category:
- Microcontrollers
- Package:
- 56-PowerTSSOP (0.240", 6.10mm Width)
- Datasheet:
-
TMX5700914APGEQQ1.pdf
- Description:
- IC MCU 16/32B 1MB FLASH 56HTSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TMX5700914APGEQQ1 from Texas Instruments is a dual-CPU lockstep ARM Cortex-R4F 32-bit safety microcontroller for automotive ASIL-D and IEC 61508 SIL-3 applications. It delivers 265 DMIPS at 160 MHz, integrates 1 MB flash with ECC, 128 KB RAM with ECC, and supports triple CAN (DCAN), dual 12-bit MibADCs (24+16 channels), seven ePWM modules, and two N2HET timing coprocessors. It is deployed in electric power steering and braking systems requiring real-time deterministic control and fault containment.
For engineers reviewing the TMX5700914APGEQQ1 datasheet, TMX5700914APGEQQ1 pinout, TMX5700914APGEQQ1 application, or TMX5700914APGEQQ1 equivalent, key selection criteria include lockstep CPU architecture, FMPLL clocking with slip detection, integrated ESM error signaling, and functional safety certification evidence for ISO 26262 ASIL-D development workflows.
Technical Context
The TMX5700914APGEQQ1 implements dual Cortex-R4F CPUs executing identical instructions in lockstep with hardware comparator monitoring; any divergence triggers ESM fault signaling via nERROR. Its memory subsystem applies ECC to 1 MB flash and 128 KB SRAM, while peripheral memories-including MibADC buffers and MibSPI RAM-use parity protection.
Real-time peripherals are hardware-protected: DMA uses dedicated MPU and parity-protected control RAM; N2HET modules include HTU with built-in MPU; ePWM features trip-zone inputs and synchronization with MibADC; and DCAN controllers support full CAN 2.0B at up to 1 Mbps with 64 mailboxes each.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-R4F dual-core lockstep, 1.66 DMIPS/MHz, up to 160 MHz → 265 DMIPS deterministic execution |
| Memory | 1 MB flash with ECC + 64 KB emulated EEPROM with ECC + 128 KB RAM with ECC → certified data integrity for safety-critical code/data storage |
| ADC | Dual 12-bit MibADC: ADC1 (24 ch), ADC2 (16 ch), 16 shared channels, 64-word parity-protected buffer each → synchronized high-resolution sensing for motor current/voltage feedback |
| PWM & Timing | 7 ePWM modules (14 outputs), 6 eCAP, 2 eQEP, 2 N2HET (32+18 channels) → precise gate drive, encoder interface, and programmable waveform generation for inverter control |
| Communication | 3 DCAN (CAN 2.0B, 64 mailboxes each), 3 MibSPI (128-word parity RAM), 2 SCI (1 LIN 2.1), 1 I2C → robust multi-bus connectivity for distributed vehicle networks |
| Safety Features | Built-in self-test (BIST) for CPU/RAM, voltage/clock monitoring, FMPLL slip detector, ESM with nERROR pin → hardware-enforced diagnostic coverage per ISO 26262 requirements |
| Supply | Core VCC: 1.14–1.32 V; I/O VCCIO: 3.0–3.6 V → separate low-noise core domain and flexible I/O interfacing |
Pinout & Package
LQFP-144 (PGE) package, 20.0 mm × 20.0 mm body size, green RoHS-compliant finish. Pinout defined per TI SPNS225D datasheet Section 4.1.1 and Table 4-1–4-20.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| nPORRST | Power-on reset input | Active-low asynchronous reset asserted during power ramp; disables all I/O buffers until release |
| nERROR | Error signaling output | Open-drain active-low fault indicator driven by ESM on CPU mismatch, memory error, or clock/voltage violation |
| GIOA[0]–GIOA[7], GIOB[0]–GIOB[7] | General-purpose I/O | Up to 64 total GIO pins; 10 support interrupt generation; configurable as peripheral multiplex or GPIO with pullup/pulldown |
| CAN1RX/CAN1TX, CAN2RX/CAN2TX, CAN3RX/CAN3TX | CAN transceiver interface | Three independent differential CAN bus interfaces compliant with ISO 11898-1; each supports 1 Mbps operation |
| AD1IN[0]–AD1IN[23], AD2IN[0]–AD2IN[15] | Analog input terminals | 24-channel ADC1 + 16-channel ADC2 with 16 shared inputs; referenced to ADREFHI/ADREFLO and powered by VCCAD/VSSAD |
| N2HET1[0]–N2HET1[31], N2HET2[0]–N2HET2[17] | High-end timer I/O | 44 total N2HET pins across two modules; support PWM, capture, quadrature decoding, and general-purpose timed I/O |
Key Features
| Feature | Design Value |
|---|---|
| Dual lockstep Cortex-R4F CPUs | Hardware-synchronized execution with real-time divergence detection and ESM-triggered fault response |
| ECC-protected memory subsystem | 1 MB flash and 128 KB RAM protected by single-bit correction/double-bit detection - required for ASIL-D memory safety |
| FMPLL with slip detection | Frequency-modulated PLL provides jitter-resistant clock synthesis; slip detector identifies oscillator failure or frequency deviation |
| Two N2HET timing coprocessors | N2HET1 (32 channels) + N2HET2 (18 channels) offload complex timing tasks from CPU; each includes HTU with MPU-protected memory transfers |
| Triple DCAN with 64 mailboxes | Three independent CAN controllers supporting CAN 2.0B protocol; 64 mailbox FIFOs per controller enable high-throughput message handling |
| Integrated safety monitoring | ESM monitors CPU, memory, clock, and voltage domains; asserts nERROR and optionally triggers system-level fail-safe actions |
Applications
| Electric Power Steering (EPS) | Braking Systems (ABS/ESC) |
|---|---|
Use Scenario: Real-time torque assist calculation and three-phase inverter control for brushless DC motors in column-assist EPS units. IC Role / Device Role / Timing Role: Primary safety MCU executing ASIL-D motor control algorithms, managing ePWM deadtime, sampling current sensors via MibADC, and communicating over CAN to vehicle network. Use Value: Lockstep CPU and ECC memory ensure fault-free execution of torque commands; N2HET handles precise PWM edge timing independent of CPU load. |
Use Scenario: Closed-loop hydraulic pressure modulation and wheel-speed-based intervention logic in anti-lock braking and electronic stability control modules. IC Role / Device Role / Timing Role: Safety-certified controller coordinating solenoid valve actuation (via ePWM), ABS sensor acquisition (via eCAP/eQEP), and CAN messaging with brake ECUs. Use Value: Triple DCAN enables redundant communication paths; BIST and ESM provide runtime diagnostics meeting ISO 26262 ASIL-D FMEDA targets. |
| HEV/EV Inverter Control | Battery Management Systems (BMS) |
Use Scenario: High-frequency switching control of IGBT/SiC power stages in traction inverters, including phase current sensing, temperature monitoring, and fault shutdown. IC Role / Device Role / Timing Role: Real-time safety controller running field-oriented control (FOC), synchronizing ePWM outputs with MibADC sampling, and validating sensor data integrity. Use Value: 128 KB ECC RAM stores FOC coefficients and calibration tables; FMPLL ensures stable timing under voltage transients common in high-power EV environments. |
Use Scenario: Cell voltage, temperature, and current monitoring with isolation interface management and SOC/SOH estimation in high-voltage battery packs. IC Role / Device Role / Timing Role: Safety gateway MCU aggregating analog measurements (MibADC), communicating with isolated slave monitors (via SPI/I2C), and reporting status over CAN. Use Value: Parity-protected MibSPI RAM ensures reliable command transmission to isolated ADCs; dual MibADCs enable simultaneous cell-group sampling for fast transient detection. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar safety microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TMS570LS1227ZWT | 337-ball BGA, 180 MHz, 1280 KB flash, 192 KB RAM, 2× EMAC, 2× FlexRay - no LIN/SCI UART mode | Targeted at chassis domain controllers requiring Ethernet/FlexRay backbone connectivity, not LIN-peripheral integration | Select when Ethernet or FlexRay physical layer support is mandatory and board space allows BGA packaging. |
| TMS570LS0432PZ | 100-pin LQFP, 80 MHz, 384 KB flash, 32 KB RAM, 2× CAN, 1× eQEP, 1× N2HET (19 ch), no I2C | Lower-cost entry-level variant for non-ASIL-D or lower-performance safety functions (e.g., HVAC control, lighting) | Choose for cost-sensitive designs where reduced memory, peripheral count, and clock speed meet functional safety requirements. |
Compared with TMX5700914APGEQQ1, TMS570LS1227ZWT offers higher performance and networking capability but requires BGA assembly and lacks LIN; TMS570LS0432PZ reduces footprint and cost but sacrifices flash capacity, ADC channel count, and N2HET flexibility - making it unsuitable for full ASIL-D inverter control.
Availability
TMX5700914APGEQQ1 is available at Aetrix Electronics and suitable for electric power steering, braking systems, and HEV/EV inverter control requiring stable component supply across long-life automotive programs.
Supply support for TMX5700914APGEQQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies with deep expertise in automotive functional safety solutions.
The Hercules TMS570 family - including TMX5700914APGEQQ1 - was designed specifically for ISO 26262 ASIL-D and IEC 61508 SIL-3 safety-critical applications in automotive, industrial, and transportation systems.
FAQ
What safety certifications apply to the TMX5700914APGEQQ1?
The TMX5700914APGEQQ1 is qualified for automotive applications per AEC-Q100 Grade 1 and supports ISO 26262 ASIL-D development with documented FMEDA, safety manuals, and diagnostic software libraries. TI provides certified compiler toolchains and safety documentation packages specifically for TMX5700914APGEQQ1 to accelerate functional safety certification.
Does the TMX5700914APGEQQ1 support LIN 2.1 communication?
Yes, the TMX5700914APGEQQ1 includes one SCI module that supports Local Interconnect Network (LIN) 2.1 protocol in addition to standard UART operation. This SCI can be configured as a LIN master or slave and complies with LIN 2.1 physical layer specifications, enabling direct connection to LIN sensors and actuators without external transceivers.
How many CAN interfaces does the TMX5700914APGEQQ1 support?
The TMX5700914APGEQQ1 integrates three independent DCAN controllers compliant with CAN 2.0A and 2.0B protocols. Each DCAN supports bit rates up to 1 Mbps and includes 64 dedicated mailboxes with parity protection, enabling robust multi-bus communication for distributed automotive networks.
What is the purpose of the N2HET modules in the TMX5700914APGEQQ1?
The TMX5700914APGEQQ1 includes two Next-Generation High-End Timer (N2HET) modules - N2HET1 (32 channels) and N2HET2 (18 channels) - designed to offload precise timing-critical tasks from the main CPU. They execute microcoded instructions to generate PWM waveforms, capture encoder edges, implement quadrature decoding, and manage complex I/O sequencing independently.
Can the TMX5700914APGEQQ1 operate with a single power supply?
No, the TMX5700914APGEQQ1 requires two separate supply domains: core voltage (VCC = 1.14–1.32 V) for CPU and memory, and I/O voltage (VCCIO = 3.0–3.6 V) for peripheral interfaces. These must be independently regulated; mixing supplies violates absolute maximum ratings and compromises ECC functionality and I/O signal integrity.
TMX5700914APGEQQ1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 56-PowerTSSOP (0.240", 6.10mm Width)
- Series:
- Hercules™ TMS570 ARM® Cortex®-R
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-R4F
- Core Size:
- 16/32-Bit
- Speed:
- 160MHz
- Connectivity:
- CANbus, I2C, LINbus, MibSPI, SCI, SPI, UART/USART
- Peripherals:
- DMA, POR, PWM, WDT
- Number of I/O:
- 64
- Program Memory Size:
- 1MB (1M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.14V ~ 3.6V
- Data Converters:
- A/D 24x12b, 16x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
TMX5700914APGEQQ1 FAQ
1.How can I place an order for TMX5700914APGEQQ1 through Aetrix?
Please submit a Request for Quotation (RFQ) for TMX5700914APGEQQ1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TMX5700914APGEQQ1 reliable?
The price and inventory of TMX5700914APGEQQ1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TMX5700914APGEQQ1 is usually 5 days.
3.What payment methods are accepted for TMX5700914APGEQQ1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TMX5700914APGEQQ1 transactions.
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4.How is shipping managed for TMX5700914APGEQQ1?
TMX5700914APGEQQ1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TMX5700914APGEQQ1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TMX5700914APGEQQ1?
For technical support, including TMX5700914APGEQQ1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TMX5700914APGEQQ1 requirements.
6.How does Aetrix verify that TMX5700914APGEQQ1 is sourced from the original manufacturer or authorized distributors?
All TMX5700914APGEQQ1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TMX5700914APGEQQ1 meets industry standards.
7.What is the process for return or replacement of TMX5700914APGEQQ1?
All TMX5700914APGEQQ1 units undergo pre-shipment inspection (PSI). If there is an issue with TMX5700914APGEQQ1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TMX5700914APGEQQ1 part is unused and in its original packaging.
Return procedure for TMX5700914APGEQQ1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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