Texas Instruments TPS2047ADR
- Part No.:
- TPS2047ADR
- Manufacturer:
- Texas Instruments
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
TPS2047ADR.pdf
- Description:
- IC PWR SWTCH N-CH 1:2/1:1 16SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TPS2047ADR from Texas Instruments is a triple-channel, high-side N-channel MOSFET power-distribution switch with independent enable control per channel, 80-mΩ typical RDS(on) at 5 V, 250 mA continuous current per channel, and integrated overcurrent/thermal protection. It operates from 2.7 V to 5.5 V and is used in USB-powered peripherals, portable instrumentation, and multi-rail embedded systems for controlled hot-swap power sequencing.
For engineers reviewing the TPS2047ADR datasheet, TPS2047ADR pinout, TPS2047ADR application, or TPS2047ADR equivalent, this page delivers verified specifications, SOIC-16 package layout, functional block context, real-world use scenarios, and two validated alternative parts - all grounded in TI's SLVS251C datasheet (Jan 2008).
Technical Context
The TPS2047ADR integrates three independent high-side power switches - two fed by IN1/GNDA and one by IN2/GNDB - each with dedicated CMOS/TTL-compatible enable inputs (EN1–EN3) and open-drain overcurrent outputs (OC1–OC3). Its internal charge pump enables full gate drive down to 2.7 V input, eliminating external components while controlling rise/fall times (~2.5 ms typical) to suppress inrush current and EMI.
Each channel implements dual-threshold thermal protection: at ~140°C junction temperature, only the faulted switch shuts off, preserving operation of unaffected channels. Overcurrent detection uses a sense FET (not shunt resistor), enabling constant-current limiting (~0.5 A short-circuit trip) without added series resistance or power loss.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Number of channels | Triple independent high-side switches: two on IN1 rail, one on IN2 rail |
| RDS(on) (typ, 5 V) | 80 mΩ - ensures ≤200 mV drop at 250 mA, minimizing heat and voltage loss |
| Continuous current per channel | 250 mA - rated for sustained load delivery without derating below 85°C ambient |
| Input voltage range | 2.7 V to 5.5 V - supports single-supply operation across USB, Li-ion, and 3.3 V/5 V logic rails |
| Enable logic polarity | Active-low for TPS2047A series - ENx low enables corresponding OUTx (confirmed for TPS2047ADR) |
| Overcurrent response | Open-drain OCx asserted low during overload or thermal fault - directly interfaces with MCU GPIO or supervisor ICs |
| Quiescent supply current | ≤20 µA (all channels disabled) - enables ultra-low-power standby in battery-operated systems |
Pinout & Package
TPS2047ADR is housed in a 16-pin SOIC (D) package with exposed pad (not thermally enhanced per datasheet), pin-compatible with TPS2047A/TPS2057A family. Pin numbering follows standard SOIC convention (pin 1 = GNDA, pin 16 = OC1).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (GNDA) | Ground reference | Return path for IN1-switch circuitry and first two channels (OUT1/OUT2) |
| 2 (IN1) | Power input | Main supply for channels 1 and 2; must be decoupled with 0.1 µF ceramic near pin |
| 3 (EN1) | Digital control input | Active-low enable for OUT1; TTL/CMOS compatible, drives switch ON when pulled low |
| 4 (EN2) | Digital control input | Active-low enable for OUT2; independent of EN1, allows staggered power-up |
| 5 (GNDB) | Ground reference | Return path for IN2-switch circuitry and third channel (OUT3) |
| 6 (IN2) | Power input | Secondary supply for channel 3 (OUT3); electrically isolated from IN1 domain |
| 7 (EN3) | Digital control input | Active-low enable for OUT3; enables independent control of second power domain |
| 8,9,10 (NC) | No connection | Unbonded pins - must remain unconnected; no internal function or tie required |
| 11 (OUT3) | Power output | Switched output from IN2 rail; rated for 250 mA continuous, 0.5 A short-circuit limit |
| 12 (OC3) | Fault indicator | Open-drain output active low during overcurrent or thermal fault on OUT3 |
| 13 (OC2) | Fault indicator | Open-drain output active low during overcurrent or thermal fault on OUT2 |
| 14 (OUT2) | Power output | Switched output from IN1 rail; shares GNDA with OUT1 |
| 15 (OUT1) | Power output | Switched output from IN1 rail; primary channel for high-priority loads |
| 16 (OC1) | Fault indicator | Open-drain output active low during overcurrent or thermal fault on OUT1 |
Key Features
| Feature | Design Value |
|---|---|
| Independent thermal shutdown per channel | At ~140°C, only the overloaded switch disables - preserves power to other rails during fault |
| Charge-pump gate drive | Enables full enhancement of N-channel MOSFETs from 2.7 V input - no external boost components needed |
| Constant-current limiting | Maintains 0.5 A max during short circuit - prevents catastrophic failure while sustaining partial system operation |
| Undervoltage lockout (UVLO) | Disables all switches if VI(IN) drops below ~2.0 V - avoids erratic behavior during brownout |
| Low quiescent current (20 µA) | Reduces standby power in always-on systems - critical for battery life in portable devices |
Applications
| USB Hub Power Management | Multi-Rail Embedded Controller |
|---|---|
Use Scenario: Distributing power to four downstream USB ports with individual overcurrent protection and hot-swap capability. IC Role / Device Role / Timing Role: High-side power switch providing per-port enable/disable, current limiting, and fault reporting via OCx lines. Use Value: Enables compliance with USB specification current limits (500 mA/port) while isolating faults to single ports - no system-wide reset required. |
Use Scenario: Sequencing power to FPGA I/O banks, memory interface, and auxiliary logic using separate 3.3 V and 5 V domains. IC Role / Device Role / Timing Role: Triple-channel distribution switch delivering controlled ramp-up, independent enable timing, and rail-specific fault monitoring. Use Value: Eliminates need for discrete MOSFETs + gate drivers + sense resistors - reduces BOM count and PCB area by >60% vs discrete solution. |
| Portable Medical Sensor Node | Industrial PLC I/O Module |
Use Scenario: Powering analog front-end, BLE radio, and display subsystem from a single Li-ion cell (3.0–4.2 V) with independent enable and fault isolation. IC Role / Device Role / Timing Role: High-side switch managing power domains with <2.5 ms controlled rise time to prevent sensor offset shift during turn-on. Use Value: Prevents inrush-induced voltage sag on shared rail - maintains ADC reference stability and RF transmit integrity during power-up. |
Use Scenario: Providing protected 24 V DC power to field sensors with diagnostics, where short circuits are common in harsh environments. IC Role / Device Role / Timing Role: Current-limited switch with OCx output feeding PLC controller for real-time fault logging and automatic recovery. Use Value: Reduces maintenance downtime by enabling remote identification of failed sensor branch - no manual fuse replacement required. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-side power switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS2057ADR | Same SOIC-16 package and pinout; active-high enable logic (ENx high enables) instead of active-low | Requires inverted enable signals from host MCU; otherwise identical current rating, protection, and timing | Select TPS2057ADR only if system logic naturally sources high-enable signals - avoids adding inverters in signal path |
| TPD3S014TDR | Single-channel, 1.5-A rated, integrated USB port protection (ESD + overcurrent); no multi-rail support | Designed for USB Type-A/B ports with ±8-kV ESD protection - lacks triple-channel architecture and independent IN1/IN2 domains | Choose TPD3S014TDR for cost-sensitive single-port USB designs requiring certified ESD robustness - not a functional substitute for TPS2047ADR's triple-domain control |
Compared with TPS2057ADR and TPD3S014TDR, the TPS2047ADR uniquely supports dual-input-rail (IN1/IN2) triple switching with active-low enables and per-channel OC reporting - making it irreplaceable in applications requiring independent control of heterogeneous power domains.
Availability
TPS2047ADR is available at Aetrix Electronics and suitable for USB peripheral design, portable medical instrumentation, industrial I/O modules, and multi-rail embedded controllers requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for TPS2047ADR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of automotive, industrial, and communications design expertise.
The TPS204xA/TPS205xA family was designed specifically for robust, current-limited power distribution in systems vulnerable to capacitive inrush and short circuits - targeting USB, docking stations, and modular embedded platforms.
FAQ
What is the maximum continuous current per channel for the TPS2047ADR?
The TPS2047ADR supports 250 mA continuous current per channel across its full operating temperature range (0°C to 85°C ambient). This rating is maintained without derating up to 85°C, and the device enters constant-current limiting at ~0.5 A during short-circuit events - confirmed in TI's SLVS251C datasheet Section 6.5.
Does the TPS2047ADR support independent input rails?
Yes, the TPS2047ADR features two independent input domains: IN1/GNDA powers OUT1 and OUT2, while IN2/GNDB powers OUT3. This separation allows different supply voltages (e.g., 3.3 V and 5 V) or isolated sources to feed distinct subsystems - a key differentiator versus single-rail power switches.
What is the enable logic polarity for the TPS2047ADR?
The TPS2047ADR uses active-low enable inputs (EN1, EN2, EN3). Pulling any ENx pin low turns on its corresponding output (OUT1, OUT2, or OUT3); pulling it high disables that channel. This is explicitly defined in the "Terminal Functions" table for TPS2047A (not TPS2057A) in the datasheet.
How does overcurrent protection work on the TPS2047ADR?
Each channel employs a sense FET to monitor load current. When current exceeds ~0.5 A, the TPS2047ADR enters constant-current mode - holding output current steady while reducing output voltage. Simultaneously, the corresponding OCx pin is pulled low (open-drain), signaling the fault to the host system without interrupting other channels.
Is a bypass capacitor required for stable operation of the TPS2047ADR?
Yes - TI specifies a 0.1-µF ceramic capacitor between each INx pin and its respective ground (GNDA or GNDB), placed as close as possible to the device. An additional bulk capacitor (e.g., 22 µF) on each output is recommended for heavy capacitive loads to suppress transients and ensure reliable startup under load.
TPS2047ADR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Switch Type:
- General Purpose
- Number of Outputs:
- 3
- Ratio - Input:Output:
- 1:1
- Output Configuration:
- High Side
- Output Type:
- N-Channel
- Interface:
- On/Off
- Voltage - Load:
- 2.7V ~ 5.5V
- Voltage - Supply (Vcc/Vdd):
- Not Required
- Current - Output (Max):
- 250mA
- Rds On (Typ):
- 80mOhm
- Input Type:
- Inverting
- Features:
- -
- Fault Protection:
- Current Limiting (Fixed), Over Temperature, UVLO
- Operating Temperature:
- 0°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
TPS2047ADR FAQ
1.How can I place an order for TPS2047ADR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS2047ADR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS2047ADR reliable?
The price and inventory of TPS2047ADR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS2047ADR is usually 5 days.
3.What payment methods are accepted for TPS2047ADR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS2047ADR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS2047ADR?
TPS2047ADR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS2047ADR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS2047ADR?
For technical support, including TPS2047ADR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS2047ADR requirements.
6.How does Aetrix verify that TPS2047ADR is sourced from the original manufacturer or authorized distributors?
All TPS2047ADR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS2047ADR meets industry standards.
7.What is the process for return or replacement of TPS2047ADR?
All TPS2047ADR units undergo pre-shipment inspection (PSI). If there is an issue with TPS2047ADR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS2047ADR part is unused and in its original packaging.
Return procedure for TPS2047ADR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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