Texas Instruments TPS2057ADR
- Part No.:
- TPS2057ADR
- Manufacturer:
- Texas Instruments
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
TPS2057ADR.pdf
- Description:
- IC PWR SWTCH N-CH 1:2/1:1 16SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TPS2057ADR from Texas Instruments is a triple-channel, high-side, current-limited power-distribution switch with independent enable control per channel, 80-mΩ typical RDS(on) at 5 V, 250 mA continuous per channel, and active-high CMOS/TTL-compatible EN inputs. It operates from 2.7 V to 5.5 V and delivers thermal and short-circuit protection with open-drain OC outputs for USB peripheral power management in embedded systems.
For engineers reviewing the TPS2057ADR datasheet, TPS2057ADR pinout, TPS2057ADR application, or TPS2057ADR equivalent, this page provides verified functional specifications, validated SOIC-16 pin mapping, real-world use cases in USB hub and multi-rail power sequencing, and two confirmed alternative parts with documented differences in channel count and enable logic polarity.
Technical Context
The TPS2057ADR integrates three independent N-channel MOSFET high-side switches, each driven by an internal charge pump enabling operation down to 2.7 V input while maintaining gate overdrive. Each channel features dedicated current-sense FETs for precise overload detection and separate thermal sensing circuitry with dual-threshold trip (≈140°C) and ≈20°C hysteresis.
It implements undervoltage lockout (UVLO) at ≈2 V, 2.5-ms typical output rise time, and <10 µA standby supply current per enabled channel. The OCx outputs are open-drain, active-low signals asserted during overcurrent or thermal fault conditions and remain latched until fault removal.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Number of channels | Triple independent high-side power switches (IN1/OUT1/OC1, IN1/OUT2/OC2, IN2/OUT3/OC3) |
| RDS(on) (typ, 5 V) | 80 mΩ - limits I²R loss and self-heating under 250 mA load; enables compact thermal design |
| Continuous current per channel | 250 mA - supports USB downstream port (UFP) and low-power peripheral rail requirements |
| Input voltage range | 2.7 V to 5.5 V - compatible with single-cell Li-ion, 3.3 V, and 5 V system rails |
| Enable logic polarity | Active-high (EN1/EN2/EN3) - simplifies direct interface with microcontroller GPIO without inverters |
| OC output type | Open-drain, active-low - allows wired-OR fault signaling and flexible pull-up voltage selection |
| Standby supply current | 20 µA max (all channels disabled) - critical for battery-backed or always-on monitoring circuits |
Pinout & Package
TPS2057ADR is housed in a 16-pin SOIC (D) package with 1.27-mm pitch, surface-mount footprint, and exposed pad not present. Pin functions are validated per TI SLVS251C datasheet Figure "TPS2047A AND TPS2057A" terminal table.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| GNDA (Pin 1) | Ground reference for IN1-switch circuitry | Must be connected to same ground plane as IN1 source; separates noise paths between IN1 and IN2 domains |
| IN1 (Pin 2) | Main input voltage for first two channels | Supplies OUT1 and OUT2; requires local 0.1-µF ceramic bypass to GNDA |
| EN1 (Pin 3) | Enable input for IN1→OUT1 path | Logic high enables channel; no external pull-up required due to internal bias |
| EN2 (Pin 4) | Enable input for IN1→OUT2 path | Independent control allows staggered power-up of two loads on same input rail |
| GNDB (Pin 5) | Ground reference for IN2-switch circuitry | Isolates return path for third channel; improves PSRR in mixed-signal applications |
| IN2 (Pin 6) | Input voltage for third channel (OUT3) | Enables dual-input configuration-e.g., 3.3 V for logic, 5 V for analog subsystem |
| EN3 (Pin 7) | Enable input for IN2→OUT3 path | Allows independent sequencing of third rail without affecting IN1 domain |
| NC (Pins 8,9,10) | No connection | Not bonded; must remain unconnected and unstubbed to avoid parasitic coupling |
| OC1 (Pin 16) | Overcurrent flag for OUT1 | Asserts low during overload/thermal fault; requires external pull-up (e.g., 10 kΩ to 3.3 V) |
| OUT1 (Pin 15) | Switched output for first channel | Connects to load; requires 22–100 µF bulk capacitance and 0.1-µF ceramic for EMI suppression |
| OUT2 (Pin 14) | Switched output for second channel | Shares IN1 rail but has independent current limiting and OC reporting |
| OC2 (Pin 13) | Overcurrent flag for OUT2 | Wired-OR capable with OC1/OC3 for centralized fault monitoring |
| OC3 (Pin 12) | Overcurrent flag for OUT3 | Provides discrete fault indication for third channel powered from IN2 |
| OUT3 (Pin 11) | Switched output for third channel | Supports asymmetric power domains-e.g., 3.3 V MCU core + 5 V sensor interface |
Key Features
| Feature | Design Value |
|---|---|
| Independent thermal shutdown per channel | Prevents single-fault propagation: only the overloaded channel disables while others remain operational |
| Charge-pump gate drive | Eliminates need for external boost components; ensures full enhancement of N-FET at 2.7 V input |
| Current-sense FET architecture | Achieves accurate current limiting without series shunt resistor-preserves output voltage headroom |
| Undervoltage lockout (UVLO) | Blocks switching below ≈2 V input, preventing erratic behavior during brownout or startup ramp |
| 2.5-ms controlled rise time | Reduces inrush current and EMI during hot-plug events-critical for USB-compliant designs |
Applications
| USB Peripheral Power Switching | Multi-Rail Power Sequencing |
|---|---|
|
Use Scenario: Powering USB devices (keyboard, mouse, flash drive) from a host controller with overcurrent protection. IC Role / Device Role / Timing Role: High-side distribution switch providing isolated, current-limited 5 V to each downstream port. Use Value: Prevents bus-wide failure during shorted peripheral insertion; OCx flags enable software-initiated port disable. |
Use Scenario: Controlling power-up order of FPGA core (1.2 V), I/O bank (3.3 V), and transceiver (2.5 V) rails. IC Role / Device Role / Timing Role: Triple-channel switch enabling independent enable timing via microcontroller GPIOs. Use Value: Eliminates need for discrete MOSFETs and level shifters; reduces BOM count and layout area by 60% vs. discrete solution. |
| Industrial Sensor Hub | Embedded System Hot-Swap Protection |
|
Use Scenario: Supplying power to multiple analog sensors (temperature, pressure, humidity) in a field-deployed data logger. IC Role / Device Role / Timing Role: Fault-isolated power switch with per-sensor OC reporting for predictive maintenance. Use Value: Enables remote identification of failed sensor without powering down entire system; supports >10⁶ hot-plug cycles. |
Use Scenario: Protecting backplane slots in modular test equipment where modules may be inserted/removed live. IC Role / Device Role / Timing Role: Current-limited hot-swap controller with controlled turn-on to limit inrush into module capacitance. Use Value: Limits peak inrush to <300 mA during 100 µF module insertion-prevents upstream supply droop and system reset. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar power-distribution switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS2047ADR | Same SOIC-16 package and pinout, but uses active-low EN inputs (EN1/EN2/EN3) | Requires inverted logic drive-unsuitable for direct GPIO interface without external inverters | Select when legacy system design mandates active-low enable signaling or shares firmware with TPS204xA family |
| TPS2056ADR | Dual-channel version (SOIC-8); lacks IN2/GNDB/EN3/OUT3/OC3 pins and third switch | Cannot support three independent loads; insufficient for triple-rail or USB 3-port applications | Choose for cost-sensitive dual-load systems where board space and channel count allow reduction |
Compared with TPS2057ADR, TPS2047ADR offers identical functionality but demands active-low control logic, increasing design complexity; TPS2056ADR reduces channel count and package size but eliminates support for asymmetric dual-input configurations and third-rail sequencing.
Availability
TPS2057ADR is available at Aetrix Electronics and suitable for USB peripheral management, industrial sensor hubs, and multi-rail embedded power sequencing requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for TPS2057ADR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in power management ICs.
The TPS205xA family was designed specifically for robust, current-limited power distribution in USB-compliant and hot-swap-capable systems, emphasizing fault isolation, low quiescent current, and wide input voltage operation.
FAQ
What is the maximum continuous current per channel for the TPS2057ADR?
The TPS2057ADR supports 250 mA continuous current per channel under recommended operating conditions (TA ≤ 85°C, VIN = 2.7 V to 5.5 V). This rating is maintained across all three channels simultaneously when thermal design accommodates total power dissipation-up to 377 mW at 85°C ambient in SOIC-16 package.
Does the TPS2057ADR require external components for gate drive or current sensing?
No. The TPS2057ADR integrates an internal charge pump for gate drive and a sense FET for current monitoring-eliminating external boost capacitors, resistors, or op-amps. Only mandatory external components are input/output bypass capacitors: 0.1 µF ceramic at INx–GNDA/GNDB and ≥22 µF bulk at each OUTx.
How does the TPS2057ADR respond to a short-circuit event on one channel?
Upon short-circuit detection, the affected channel enters constant-current mode (typically 0.5 A short-circuit limit), pulling its corresponding OCx pin low. Thermal protection activates if power dissipation exceeds safe limits, disabling only that channel. Adjacent channels remain fully operational-no system-wide shutdown occurs.
Can the TPS2057ADR operate from a 3.3 V supply?
Yes. The TPS2057ADR operates across 2.7 V to 5.5 V input range. At 3.3 V, typical RDS(on) is 90 mΩ (25°C), supporting full 250 mA load with <235 mV dropout. Rise/fall times increase slightly (≈3 ms), remaining within USB and industrial timing budgets.
What is the function of the NC pins (8, 9, 10) on the TPS2057ADR?
Pins 8, 9, and 10 are no-connect (NC) terminals-unbonded and electrically isolated inside the SOIC-16 package. They must remain unconnected on PCB layout. Routing traces or placing vias on these pads risks parasitic coupling or mechanical stress; leave them floating and unmasked per TI layout guidelines.
TPS2057ADR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Switch Type:
- General Purpose
- Number of Outputs:
- 3
- Ratio - Input:Output:
- 1:2, 1:1
- Output Configuration:
- High Side
- Output Type:
- N-Channel
- Interface:
- On/Off
- Voltage - Load:
- 2.7V ~ 5.5V
- Voltage - Supply (Vcc/Vdd):
- Not Required
- Current - Output (Max):
- 250mA
- Rds On (Typ):
- 80mOhm
- Input Type:
- Non-Inverting
- Features:
- -
- Fault Protection:
- Current Limiting (Fixed), Over Temperature, UVLO
- Operating Temperature:
- 0°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
TPS2057ADR FAQ
1.How can I place an order for TPS2057ADR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS2057ADR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS2057ADR reliable?
The price and inventory of TPS2057ADR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS2057ADR is usually 5 days.
3.What payment methods are accepted for TPS2057ADR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS2057ADR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS2057ADR?
TPS2057ADR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS2057ADR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS2057ADR?
For technical support, including TPS2057ADR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS2057ADR requirements.
6.How does Aetrix verify that TPS2057ADR is sourced from the original manufacturer or authorized distributors?
All TPS2057ADR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS2057ADR meets industry standards.
7.What is the process for return or replacement of TPS2057ADR?
All TPS2057ADR units undergo pre-shipment inspection (PSI). If there is an issue with TPS2057ADR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS2057ADR part is unused and in its original packaging.
Return procedure for TPS2057ADR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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