Texas Instruments TPS2066DRG4
- Part No.:
- TPS2066DRG4
- Manufacturer:
- Texas Instruments
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
TPS2066DRG4.pdf
- Description:
- IC PWR SWITCH N-CHAN 1:2 8SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TPS2066DRG4 from Texas Instruments is a dual-channel, current-limited, high-side power-distribution switch featuring two 70 mΩ N-channel MOSFETs, 1 A continuous output per channel, thermal and short-circuit protection, and operation from 2.7 V to 5.5 V. It delivers precise current limiting (1.1 A min / 1.9 A max), built-in soft-start, and deglitched OC reporting-used in USB-powered peripherals and industrial I/O modules requiring robust fault management.
For engineers reviewing the TPS2066DRG4 datasheet, TPS2066DRG4 pinout, TPS2066DRG4 application, or TPS2066DRG4 equivalent, this page provides verified functional specifications, validated dual-channel switching behavior, confirmed SOIC-8 package mapping, and real-world design implications for capacitive-load management and overcurrent recovery timing.
Technical Context
The TPS2066DRG4 integrates two independent high-side N-MOSFET switches with internal charge-pump gate drive enabling full conduction down to 2.7 V input. Each channel features dedicated enable inputs (EN1/EN2 active-high) and open-drain overcurrent outputs (OC1/OC2), supporting asynchronous fault monitoring without shared logic dependencies.
Its flat current-limit profile-distinct from peaking-type variants like TPS2063-holds output current at ~1.5 A typical under overload, with no separate trip threshold; thermal shutdown activates only after sustained overcurrent raises junction temperature beyond 135°C, recovering automatically at 125°C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Channel count | Dual independent high-side switches-enables isolated power control for two downstream rails (e.g., USB VBUS + auxiliary 3.3V rail) |
| rDS(on) | 70 mΩ typical (D package, 5 V, 1 A)-minimizes conduction loss and self-heating during 1 A continuous operation |
| Current limit | 1.1 A min / 1.9 A max (–40°C to 125°C)-guarantees safe inrush handling for ≥100 µF loads while avoiding nuisance tripping |
| Rise time (tr) | 0.6 ms typical (5.5 V, 1 µF load)-controls dI/dt to suppress EMI and reduce voltage droop on shared input rails |
| Supply current (disabled) | ≤1 µA max (–40°C to 125°C)-enables ultra-low-power standby in battery-backed systems without external disconnect |
| UVLO threshold | 2.0 V to 2.6 V rising edge (75 mV hysteresis)-prevents erratic switching during brownout or cold-start conditions |
| Thermal shutdown | 135°C activation / 125°C recovery (10°C hysteresis)-protects silicon integrity during sustained short-circuit faults |
Pinout & Package
TPS2066DRG4 uses an 8-pin SOIC (D) package with exposed PowerPAD™ thermally connected to GND. Pin 1 is EN1, Pin 2 is IN, Pin 3 is EN2, Pin 4 is GND, Pin 5 is OC2, Pin 6 is OUT2, Pin 7 is OUT1, Pin 8 is OC1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| EN1 (Pin 1) | Logic enable input for Channel 1 | Active-high signal; drives internal charge pump and gate driver when pulled ≥2 V-no external pull-up required |
| IN (Pin 2) | Common input voltage supply | Shared 2.7–5.5 V source for both channels; must be decoupled locally to handle simultaneous turn-on transients |
| EN2 (Pin 3) | Logic enable input for Channel 2 | Independent control of second switch; enables staggered power-up sequencing to avoid input rail collapse |
| GND (Pin 4) | Ground reference and thermal pad connection | Primary return path; PowerPAD™ must be soldered to ≥1 cm² copper pour for RθJB = 59.6°C/W thermal performance |
| OC2 (Pin 5) | Open-drain overcurrent flag for Channel 2 | Active-low assertion (≤0.4 V @ 5 mA) with 4–15 ms deglitch-rejects noise spikes but responds to true shorts within 15 ms |
| OUT2 (Pin 6) | Channel 2 power-switch output | Drives load directly; reverse leakage <1 µA ensures no backfeed when disabled and OUT2 > IN |
| OUT1 (Pin 7) | Channel 1 power-switch output | Electrically isolated from OUT2; supports independent load types (e.g., motor + sensor) without cross-talk |
| OC1 (Pin 8) | Open-drain overcurrent flag for Channel 1 | Asynchronous fault reporting-allows microcontroller to poll OC1/OC2 separately or wire-OR them for single-interrupt alert |
Key Features
| Feature | Design Value |
|---|---|
| Built-in soft-start | Controls dV/dt on OUT1/OUT2 to limit inrush surge-enables safe hot-plug into 100 µF+ capacitive loads without input rail sag |
| Accurate current limit | Guaranteed 1.1–1.9 A window across –40°C to 125°C-eliminates need for external current-sense resistors or calibration |
| Deglitched OC reporting | 4–15 ms filter on OC1/OC2 pins prevents false triggers from transient noise or ESD events during normal switching |
| No OC glitch at power-up | OC outputs remain high-Z until internal bias stabilizes-avoids spurious MCU interrupts during system boot |
| UL listed (E169910) | Meets UL 60950-1 end-equipment safety requirements-reduces certification burden for industrial and medical designs |
Applications
| USB Peripheral Power Switching | Industrial Digital I/O Module |
|---|---|
|
Use Scenario: Hot-plugging USB devices (e.g., printers, storage) into embedded hosts where bus voltage must remain stable during insertion. IC Role / Device Role / Timing Role: Dual-channel high-side switch isolating VBUS and auxiliary 3.3V rails; enables independent enable/disable with sub-millisecond rise/fall control. Use Value: Prevents host VBUS collapse during 100 µF+ device inrush; OC1/OC2 flags allow firmware to disable faulty ports before thermal shutdown occurs. |
Use Scenario: Protecting programmable logic controller (PLC) digital outputs against field-wiring shorts or motor stall conditions. IC Role / Device Role / Timing Role: Two independent protected power paths-one for sink-type outputs, one for source-type-each with dedicated OC feedback. Use Value: Enables real-time fault isolation without system reset; flat current limit holds output at 1.5 A during short, allowing safe diagnostics before thermal shutdown. |
| Embedded System Power Sequencing | Point-of-Load (POL) Protection |
|
Use Scenario: Controlled power-up of FPGA I/O banks and memory interfaces where staggered rail activation avoids simultaneous inrush. IC Role / Device Role / Timing Role: Dual-channel switch with independent EN1/EN2 inputs-supports precise timing between 3.3V and 1.8V domain activation. Use Value: Eliminates need for discrete MOSFETs, gate drivers, and sense resistors; built-in soft-start ensures monotonic voltage ramp on each rail. |
Use Scenario: Adding overcurrent protection to DC-DC converter outputs feeding sensitive analog or RF circuitry. IC Role / Device Role / Timing Role: High-side protector placed downstream of buck regulator; monitors load current independently of upstream controller. Use Value: Adds fail-safe current limiting without affecting regulator loop stability; 70 mΩ rDS(on) introduces <50 mV drop at 700 mA-within most POL tolerance bands. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel power-switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS2062DR | Same SOIC-8 package and pinout; identical electrical specs except EN1/EN2 are active-low (vs. active-high on TPS2066DRG4) | Requires inverted enable logic-unsuitable for direct replacement if host MCU GPIOs lack configurable polarity or pull-down capability | Select TPS2062DR only when existing firmware or hardware already implements active-low enable signaling. |
| TPS2052BDR | Lower 0.5 A current rating; 150 mΩ rDS(on); no thermal shutdown-only short-circuit current limiting | Lacks thermal protection and higher current capacity; not suitable for sustained 1 A loads or environments >85°C ambient | Choose TPS2052BDR only for cost-sensitive, low-power applications where thermal risk is mitigated by external derating or enclosure cooling. |
Compared with TPS2066DRG4, TPS2062DR requires no schematic change but mandates firmware logic inversion, whereas TPS2052BDR reduces BOM cost at the expense of thermal safety margin and peak current capability-making TPS2066DRG4 optimal for unattended or high-reliability 1 A applications.
Availability
TPS2066DRG4 is available at Aetrix Electronics and suitable for USB peripheral power management, industrial I/O protection, and embedded power sequencing requiring stable component supply and long-term production continuity.
Supply support for TPS2066DRG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in high-reliability power-switching solutions.
The TPS206x family was designed specifically for robust, low-EMI power distribution in USB-compliant and industrial control systems-emphasizing integrated protection, predictable current limiting, and simplified layout over discrete alternatives.
FAQ
What is the maximum continuous current per channel for the TPS2066DRG4?
The TPS2066DRG4 supports 1 A continuous output current per channel across its full operating temperature range (–40°C to 85°C ambient). This rating assumes proper PCB thermal design-specifically, soldering the PowerPAD™ to ≥1 cm² of 2-oz copper-to maintain junction temperature below 125°C under worst-case load and ambient conditions. The device will enter thermal shutdown above 135°C if sustained overload exceeds this limit.
Does the TPS2066DRG4 support bidirectional current flow?
No, the TPS2066DRG4 is a unidirectional high-side switch. Its N-channel MOSFET architecture blocks reverse current from OUT to IN when disabled. While the datasheet mentions "bidirectional switch" in a generic family description, that statement applies only to specific variants (e.g., TPS2061 with internal back-to-back FETs); the TPS2066DRG4 has a single N-FET per channel and does not support reverse conduction.
How does the current-limiting behavior of the TPS2066DRG4 differ from the TPS2063?
The TPS2066DRG4 uses a flat current-limit profile-holding output current near 1.5 A regardless of load impedance-whereas the TPS2063 employs a peaking profile with distinct overcurrent trip (IOC ≈ 2.4 A) and short-circuit (IOS ≈ 1.5 A) thresholds. This means TPS2066DRG4 responds immediately to overloads with constant-current regulation, while TPS2063 allows brief higher-current surges before clamping, making TPS2066DRG4 more predictable for precision current control.
Can the OC1 and OC2 pins of the TPS2066DRG4 be wired together?
Yes, OC1 and OC2 can be wire-OR'd using a single pull-up resistor to monitor combined fault status. Since both are open-drain and active-low, either channel asserting overcurrent pulls the shared node low. However, this loses per-channel fault identification-use individual routing if diagnostic granularity (e.g., distinguishing which port failed) is required in firmware or system logging.
Is the TPS2066DRG4 RoHS compliant and lead-free?
Yes, the TPS2066DRG4 is RoHS compliant and lead-free per TI's official packaging information. The "G4" suffix denotes green (halogen-free) packaging and Pb-free terminations meeting JEDEC J-STD-020 moisture sensitivity level 3 (MSL-3) requirements. Full compliance documentation-including test reports and material declarations-is available via Texas Instruments' product folder and Quality & Environmental page.
TPS2066DRG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Switch Type:
- General Purpose
- Number of Outputs:
- 2
- Ratio - Input:Output:
- 1:2
- Output Configuration:
- High Side
- Output Type:
- N-Channel
- Interface:
- On/Off
- Voltage - Load:
- 2.7V ~ 5.5V
- Voltage - Supply (Vcc/Vdd):
- Not Required
- Current - Output (Max):
- 1A
- Rds On (Typ):
- 70mOhm
- Input Type:
- Non-Inverting
- Features:
- Status Flag
- Fault Protection:
- Current Limiting (Fixed), Over Temperature, UVLO
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
TPS2066DRG4 FAQ
1.How can I place an order for TPS2066DRG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS2066DRG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS2066DRG4 reliable?
The price and inventory of TPS2066DRG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS2066DRG4 is usually 5 days.
3.What payment methods are accepted for TPS2066DRG4?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS2066DRG4 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS2066DRG4?
TPS2066DRG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS2066DRG4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS2066DRG4?
For technical support, including TPS2066DRG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS2066DRG4 requirements.
6.How does Aetrix verify that TPS2066DRG4 is sourced from the original manufacturer or authorized distributors?
All TPS2066DRG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS2066DRG4 meets industry standards.
7.What is the process for return or replacement of TPS2066DRG4?
All TPS2066DRG4 units undergo pre-shipment inspection (PSI). If there is an issue with TPS2066DRG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS2066DRG4 part is unused and in its original packaging.
Return procedure for TPS2066DRG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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