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Texas Instruments TPS22985YFPR
- Part No.:
- TPS22985YFPR
- Manufacturer:
- Texas Instruments
- Package:
- 16-XFBGA, DSBGA
- Datasheet:
-
TPS22985YFPR.pdf
- Description:
- IC PWR SUP SELECTION 16DSBGA
- Quantity:
- Payment:
- Shipping:
Inventory:1,164
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Product details
Overview
TPS22985YFPR from Texas Instruments is a Thunderbolt™ supply selection IC for active cables, featuring dual-mode operation (Normal/Control), auto-selecting 3.3 V from two inputs (VDD1/VDD2), and delivering ≥10 mA on OUTA and ≥500 mA on OUTB with reverse current blocking. It integrates UART RX/TX level-shifting buffers and wake-on-activity logic for cable microcontrollers.
For engineers reviewing the TPS22985YFPR datasheet, TPS22985YFPR pinout, TPS22985YFPR application, or TPS22985YFPR equivalent, key selection considerations include its 2.8–19.8 V input range, HVLO/UVLO thresholds (3.55 V / 2.75 V), soft-start timing (200 µs FET enable), charge pump output (CPO), and WCSP-16 package compatibility with Thunderbolt cable retimer power sequencing.
Technical Context
The TPS22985YFPR implements a dual-path supply selector using four internal MOSFET switches (FET1–FET4) controlled by a logic core with integrated charge pump (CPO) driving gate voltages. It supports two distinct operational modes: Normal Mode (OUTA always on with valid VDD; OUTB enabled by ENB) and Control Mode (OUTB gated by RXH falling edge after ENB assertion).
Its UART interface includes level-shifted, failsafe RXH/RXC and TXC/TXH paths referenced to OUTA, with CFG/OE latching mode at power-up and serving as TXH output enable in Control Mode. Thermal shutdown activates at 125°C with 15°C hysteresis, and UVLO/HVLO thresholds ensure stable 3.3 V rail selection across varying input slew rates.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Input Range | 2.8 V to 19.8 V on VDD1 and VDD2 - supports wide-input Thunderbolt cable power architectures including 3.3 V, 5 V, and 12–15 V auxiliary rails. |
| Output Current Capability | ≥10 mA on OUTA, ≥500 mA on OUTB - enables direct powering of cable microcontrollers and CDR retimers without external boost or LDO stages. |
| UVLO / HVLO Thresholds | 2.75 V / 3.55 V (typ) - ensures robust 3.3 V supply validation with 60 mV hysteresis, preventing oscillation during marginal input transitions. |
| Switch On-Resistance | FET1/FET2: 5 Ω; FET3/FET4: 250 mΩ (max) - minimizes voltage drop and power loss under full 500 mA load on OUTB. |
| Charge Pump Output (CPO) | 7–9 V (typ) - drives internal FET gates to maintain low RDS(on) across full input voltage range without external bias. |
| UART Signal Timing | RXH→RXC / TXC→TXH propagation: ≤20 µs; rise/fall time ≤70 ns - preserves 1 Mb/s Thunderbolt control channel integrity with minimal jitter. |
| Thermal Shutdown | 125°C activation with 15°C hysteresis - protects device during sustained high-current operation in confined cable assemblies. |
Pinout & Package
TPS22985YFPR is housed in a 1.6 mm × 1.6 mm DSBGA (WCSP) package with 16 bumps (YFP), RoHS-compliant SnAgCu finish, MSL Level-1, and Q1 pin-1 orientation in tape-and-reel (3000 pcs/reel).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD1, VDD2 | Power Inputs | Dual independent supply inputs; VDD1 has priority-VDD2 only engages when VDD1 > 3.55 V and VDD2 is within 2.75–3.55 V window. |
| OUTA, OUTB | Power Outputs | Non-current-limited outputs: OUTA supplies ≥10 mA for logic/cfg bias; OUTB delivers ≥500 mA to retimer/μC core. |
| CPO | Charge Pump Output | Internal gate-drive voltage source; requires ≥2 nF capacitor to stabilize switching and ensure FET turn-on across full VDD range. |
| CFG/OE | Mode Select / TX Enable | Latched at power-up: floating = Normal Mode; grounded = Control Mode; becomes TXH output enable in Control Mode. |
| RXH, TXC | UART Host Interface | Level-shifted inputs monitored only in Control Mode; must be pulled low in Normal Mode to avoid undefined behavior. |
| RXC, TXH | UART Cable Interface | OUTA-referenced outputs; TXH goes Hi-Z when RESETZ is low, preventing bus contention during power loss. |
| ENB, RXH | Control Logic Inputs | In Control Mode: ENB rising edge initiates OUTB disable; RXH falling edge re-enables OUTB and asserts RESETZ high. |
| RESETZ | Open-Drain Reset Indicator | Active-low signal indicating OUTB is connected to valid VDD; used by cable μC to synchronize initialization sequence. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-Mode Supply Selection | Normal Mode provides fixed ENB-gated OUTB; Control Mode enables dynamic OUTB enable via RXH edge detection-critical for Thunderbolt hot-plug sequencing. |
| Reverse Current Blocking | Prevents backflow from OUTA/OUTB to VDD1/VDD2 during input dropout or sequencing-eliminates need for external Schottky diodes in compact cable designs. |
| Failsafe UART Buffering | RXC/TXH automatically enter Hi-Z or pull-low states when RESETZ is low, isolating host UART lines during cable power loss or reset events. |
| Soft-Start Switching | Four-step resistance ramp (250 µs intervals) limits inrush current into output capacitors-reduces stress on VDD sources and avoids triggering upstream current limits. |
| Integrated Charge Pump | Generates ~8 V gate drive from 3.3 V input, enabling low RDS(on) FET operation without external high-voltage bias-saves board space and BOM count. |
Applications
| Thunderbolt™ Active Cables | Notebook Computer Docking Interfaces |
|---|---|
Use Scenario: Powering embedded microcontroller and CDR retimer ICs inside Thunderbolt 3/4 passive-to-active conversion cables. IC Role / Device Role / Timing Role: Supply selector and UART interface conditioner-determines primary 3.3 V rail, sequences power to retimer, and isolates host UART during hot-plug. Use Value: Enables single-chip solution for cable-side power management and Thunderbolt link training coordination without discrete FETs or level shifters. |
Use Scenario: Managing auxiliary 3.3 V power delivery to Thunderbolt controller and USB-C PD logic in ultrabook docking stations. IC Role / Device Role / Timing Role: Dual-supply arbiter and fail-safe UART bridge-selects between system 3.3 V and adapter-derived 3.3 V, while buffering debug/CFG signals. Use Value: Eliminates risk of UART bus contention during adapter insertion/removal and ensures reliable firmware updates over cable-connected debug interfaces. |
| Desktop Thunderbolt Expansion Chassis | Industrial Thunderbolt Video Capture Systems |
Use Scenario: Providing isolated, sequenced 3.3 V to Thunderbolt retimer and FPGA-based protocol translators in PCIe expansion enclosures. IC Role / Device Role / Timing Role: High-reliability supply switcher with thermal protection-monitors dual redundant 3.3 V rails and disables outputs on overtemperature or undervoltage. Use Value: Prevents retimer latch-up or configuration corruption during unstable power conditions common in multi-rail desktop chassis environments. |
Use Scenario: Powering Thunderbolt-enabled video capture modules in ruggedized broadcast equipment requiring ESD-hardened, fail-safe signaling. IC Role / Device Role / Timing Role: ESD-protected UART buffer and supply supervisor-handles ±4.4 kV IEC 61000-4-2 contact discharge on VDD pins while maintaining UART integrity. Use Value: Meets industrial EMC requirements without adding external TVS diodes or isolation ICs, reducing layer count and assembly cost. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar supply selection and UART interface applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS22980YFPR | Single-output (OUT only), no UART buffers, no CFG/OE mode select - simpler architecture with lower quiescent current (15 µA vs 20 µA). | Targeted at basic Thunderbolt cable power switching without retimer communication needs. | Select when UART isolation and dynamic OUTB control are unnecessary; reduces BOM but sacrifices Thunderbolt link training support. |
| TPD3S014TDCR | USB Type-C port protection IC with integrated 3.3 V LDO, I2C interface, and ESD protection - no supply arbitration or UART functionality. | Designed for USB-C PD sink-side protection, not Thunderbolt supply selection or retimer interfacing. | Only suitable if application shifts from Thunderbolt to USB-C ecosystem; lacks VDD1/VDD2 arbitration and OUTA/OUTB dual-output capability. |
Compared with TPS22985YFPR, TPS22980YFPR offers reduced feature set and cost for non-communication cable use cases, while TPD3S014TDCR serves a fundamentally different interface standard and cannot replace Thunderbolt-specific supply arbitration or UART bridging functions.
Availability
TPS22985YFPR is available at Aetrix Electronics and suitable for Thunderbolt™ active cable manufacturing, notebook docking station design, and industrial video capture systems requiring stable component supply with long-term lifecycle visibility.
Supply support for TPS22985YFPR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity solutions, with decades of expertise in power management and interface ICs for high-speed serial standards.
The TPS22985YFPR belongs to TI's Thunderbolt™ cable power management product line, engineered specifically to meet Intel's specification requirements for active cable retimer power sequencing, UART isolation, and supply arbitration under thermal and ESD stress.
FAQ
What is the primary function of the TPS22985YFPR in Thunderbolt™ cable designs?
The TPS22985YFPR serves as a supply selection IC that automatically chooses a valid 3.3 V source from two inputs (VDD1/VDD2) and routes it to two outputs (OUTA/OUTB) while providing UART RX/TX level-shifting and failsafe control. In Thunderbolt™ active cables, it powers the embedded microcontroller and CDR retimer, manages power sequencing during hot-plug events, and isolates host UART lines during power loss-enabling reliable link training and firmware updates without external discrete components.
How does the TPS22985YFPR handle supply transitions when VDD1 exceeds the high-voltage lockout threshold?
When VDD1 rises above the HVLO threshold (3.55 V typ), the TPS22985YFPR opens FET1/FET3 within 20 µs (tdh) and connects OUTA/OUTB to VDD2-if VDD2 is within its valid 2.75–3.55 V window. During this transition, output overshoot (VOS ≤ 200 mV) occurs due to slew-rate-dependent delay, and outputs discharge through their loads before reconnecting to VDD2. This behavior is fully documented in the "Supply Switch-Over During HVLO" section of the TPS22985YFPR datasheet.
Can the TPS22985YFPR be used in Normal Mode and Control Mode interchangeably on the same PCB layout?
Yes-the TPS22985YFPR's mode is latched at power-up based solely on the CFG/OE pin state: floating enables Normal Mode; grounded enables Control Mode. No PCB changes are required to switch between modes-only the CFG/OE pull-up/pull-down configuration differs. However, UART pins (RXH, TXC, RXC, TXH) must be connected per mode: in Normal Mode they are unused and must be pulled low; in Control Mode they form the active failsafe UART path. The TPS22985YFPR pinout and footprint remain identical in both configurations.
What is the role of the CPO pin on the TPS22985YFPR, and what external component is required?
The CPO (Charge Pump Output) pin on the TPS22985YFPR delivers ~8 V (7–9 V typ) to drive the gates of internal FET switches, ensuring low RDS(on) across the full 2.8–19.8 V input range. A minimum 2 nF capacitor must be connected from CPO to GND to stabilize the charge pump and prevent gate drive collapse during transient loading. TI specifies 2–10 nF as the valid range; typical designs use a 4.7 nF X7R ceramic capacitor placed adjacent to the CPO pin.
Does the TPS22985YFPR provide reverse current protection, and how is it implemented?
Yes-the TPS22985YFPR provides inherent reverse current blocking from OUTA/OUTB back to VDD1/VDD2 via its internal MOSFET architecture and gate-drive control logic. When either output voltage exceeds its respective input supply (e.g., due to load capacitance discharge or external bias), the FETs are held in cutoff, preventing backflow. This eliminates the need for external reverse-blocking diodes in Thunderbolt cable designs, reducing power loss, board area, and thermal stress-confirmed by the "Reverse Current Blocking From OUT to VDD" feature in the TPS22985YFPR datasheet.
TPS22985YFPR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 16-XFBGA, DSBGA
- Series:
- Thunderbolt™
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Not For New Designs
- Switch Type:
- General Purpose
- Number of Outputs:
- 2
- Ratio - Input:Output:
- 1:2
- Output Configuration:
- High Side
- Output Type:
- -
- Interface:
- -
- Voltage - Load:
- 2.8V ~ 19.8V
- Voltage - Supply (Vcc/Vdd):
- -
- Current - Output (Max):
- -
- Rds On (Typ):
- 5Ohm (Max), 250mOhm (Max)
- Input Type:
- -
- Features:
- -
- Fault Protection:
- Reverse Current
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-DSBGA (1.6x1.6)
TPS22985YFPR FAQ
1.How can I place an order for TPS22985YFPR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS22985YFPR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS22985YFPR reliable?
The price and inventory of TPS22985YFPR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS22985YFPR is usually 5 days.
3.What payment methods are accepted for TPS22985YFPR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS22985YFPR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS22985YFPR?
TPS22985YFPR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS22985YFPR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS22985YFPR?
For technical support, including TPS22985YFPR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS22985YFPR requirements.
6.How does Aetrix verify that TPS22985YFPR is sourced from the original manufacturer or authorized distributors?
All TPS22985YFPR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS22985YFPR meets industry standards.
7.What is the process for return or replacement of TPS22985YFPR?
All TPS22985YFPR units undergo pre-shipment inspection (PSI). If there is an issue with TPS22985YFPR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS22985YFPR part is unused and in its original packaging.
Return procedure for TPS22985YFPR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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