Texas Instruments TPS25940ARVCR
- Part No.:
- TPS25940ARVCR
- Manufacturer:
- Texas Instruments
- Category:
- Current Regulation/Management
- Package:
- 20-WFQFN Exposed Pad
- Datasheet:
-
TPS25940ARVCR.pdf
- Description:
- IC ELECTRONIC FUSE 8% 20WQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TPS25940ARVCR from Texas Instruments is a 2.7–18 V eFuse power switch with true reverse current blocking, 42 mΩ typical RON, ±8% adjustable current limit (0.6–5.3 A), IMON current monitor output, and DevSleep™ mode supporting SATA Device Sleep compliance. It protects SSDs and enterprise storage systems against overcurrent, overvoltage, undervoltage, thermal fault, and reverse voltage events.
For engineers reviewing the TPS25940ARVCR datasheet, TPS25940ARVCR pinout, TPS25940ARVCR application, or TPS25940ARVCR equivalent, key selection criteria include its bidirectional FET architecture for holdup-power management, 1 μs reverse-voltage shutoff, programmable dV/dt ramp control, and UL 2367/UL60950 safety recognition for industrial and server-grade designs.
Technical Context
The TPS25940ARVCR integrates back-to-back N-channel MOSFETs to enable true reverse current blocking-triggering shutdown when V(IN) < V(OUT) − 10 mV-and supports seamless switchover to boosted backup sources. Its DevSleep mode draws only 95 μA typical quiescent current while maintaining precise current limiting at 0.55–0.8 A.
Programmable thresholds include ±2% OVP/UVLO, 15 μA disabled IQ, and 200 μA operating IQ. Fault detection is implemented via open-drain FLT and PGOOD outputs, with fast-trip response (<200 ns) and thermal shutdown at 160°C (12°C hysteresis).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.7 V to 18 V - supports 3.3 V, 5 V, 12 V, and 15 V DC bus rails in SSDs and servers. |
| RON (Typical) | 42 mΩ - enables low conduction loss (≤210 mW at 5 A) and minimal thermal rise in compact WQFN packages. |
| Current Limit Range | 0.6 A to 5.3 A (±8%) - set by external ILIM resistor; supports scalable protection across PCIe/SATA load profiles. |
| IMON Accuracy | ±8% gain (52.3 µA/A typical) - provides analog current monitoring for real-time load diagnostics without external sense resistors. |
| DevSleep IQ | 95 µA typical - meets SATA Device Sleep power budget requirements while retaining full fault detection capability. |
| Reverse Blocking Threshold | V(IN) − V(OUT) < −9.3 mV (typical) - prevents backfeed from load-side holdup capacitors into failed upstream supplies. |
| UL Recognition | UL 2367 File No. 169910 & UL60950 - certified for safe operation during single-point failure conditions in safety-critical systems. |
Pinout & Package
TPS25940ARVCR is housed in a 3.00 mm × 4.00 mm WQFN-20 package with exposed thermal pad (PowerPAD™) requiring PCB ground vias for thermal performance. Pin numbering follows top-view layout per TI SLVSCF3A Rev. March 2015.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN (Pins 9–13) | Power Input Supply | High-side input node; accepts 2.7–18 V; connects to upstream DC source or regulator output. |
| OUT (Pins 4–8) | Power Output to Load | Low-side output node; drives SSD controller, SATA PHY, or downstream logic; supports bidirectional current flow. |
| EN/UVLO (Pin 14) | Enable & UVLO Input | Active-high enable with 0.99 V threshold; also sets undervoltage lockout; pull-down resets latch on TPS25940L variant. |
| OVP (Pin 15) | Overvoltage Protection Input | Programmable OVP threshold (0.99 V typical); asserts FLT on overvoltage event; open-drain compatible. |
| DEVSLP (Pin 1) | DevSleep Mode Control | Active-high entry into low-IQ DevSleep mode (95 µA); required for SATA Device Sleep compliance. |
| ILIM (Pin 17) | Current Limit Programming | Resistor-to-GND sets ILIM; 16.9 kΩ → 5.2 A; 150 kΩ → 0.58 A; supports precise trip point tuning. |
| dVdT (Pin 18) | Output Ramp Rate Control | Capacitor-to-GND sets soft-start slew rate; 470 nF yields ~1 ms ramp to 12 V; prevents inrush-induced rail collapse. |
| IMON (Pin 19) | Current Monitor Output | Analog current-sense output (52.3 µA/A); converts to voltage via external resistor; enables real-time load telemetry. |
| FLT (Pin 20) | Fault Indicator Output | Open-drain active-low flag signaling OVP, UVLO, reverse voltage, thermal shutdown, or short-circuit fault. |
| PGOOD (Pin 2) | Power Good Output | Open-drain active-high signal indicating V(OUT) > PGTH threshold (0.99 V); de-glitched with 0.54 ms delay. |
Key Features
| Feature | Design Value |
|---|---|
| True Reverse Current Blocking | Shuts off in <1 µs when V(IN) drops below V(OUT) − 10 mV - eliminates need for external reverse-blocking diodes in holdup-capacitor systems. |
| Programmable dV/dt Control | Adjustable output ramp rate via external capacitor - ensures controlled turn-on and avoids system-level brownouts during hot-plug events. |
| SATA Device Sleep Compliance | 95 µA DevSleep IQ and dedicated DEVSLP pin - meets JEDEC MO-269B and SATA Rev. 3.3 low-power idle requirements. |
| Integrated Fast-Trip Protection | 200 ns response to overcurrent exceeding 1.5×ILIM + 0.375 A - limits energy delivered during short-circuit faults before thermal damage occurs. |
| UL-Recognized Safety Architecture | Validated under UL 2367 (File 169910) and UL60950 - guarantees safe behavior during single-point failures including ILIM resistor open/short. |
Applications
| PCIe/SATA SSD Power Management | Enterprise Server Holdup Power |
|---|---|
Use Scenario: Power delivery to 2.5-inch SATA SSDs in data center servers where backup capacitors must not discharge into failed primary rails. IC Role / Device Role / Timing Role: eFuse controller enforcing reverse-current blocking, programmable current limiting, and DevSleep entry/exit sequencing. Use Value: Prevents catastrophic backfeed during PSU failure; enables <100 ms graceful shutdown via PGOOD/FLT status signals. | Use Scenario: Redundant 12 V power path management in microservers with dual PSUs and bulk holdup capacitance. IC Role / Device Role / Timing Role: Bidirectional load switch isolating downstream loads during upstream fault, with thermal and overvoltage monitoring. Use Value: Eliminates need for discrete OR-ing diodes or ideal diode controllers; reduces BOM count and conduction losses by >60%. |
| RAID Card Hot-Swap Protection | Adapter-Powered Storage Enclosures |
Use Scenario: Hot-plug insertion of RAID controller cards into backplanes with shared 12 V supply and varying load capacitance. IC Role / Device Role / Timing Role: Soft-start-controlled power switch with dV/dt ramp and fast-trip overcurrent protection. Use Value: Prevents inrush-induced voltage droop on shared bus; detects and clears shorts within 200 ns to protect upstream converters. | Use Scenario: USB-C PD adapter-powered external SSD enclosures requiring robust overvoltage and reverse-polarity protection. IC Role / Device Role / Timing Role: Primary protection IC handling 5–20 V input range, OVP clamping, and reverse-voltage shutoff. Use Value: Accepts variable adapter voltages up to 18 V; blocks reverse current if user inserts cable backward; UL-certified for end-product safety compliance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar eFuse power switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS25942ARVCR | Same pinout, 2.7–20 V rating, 38 mΩ RON, adds I2t overcurrent protection and enhanced thermal metrics. | Supports higher input transients (20 V vs 18 V); optimized for 5G base station power modules with tighter thermal constraints. | Select TPS25942ARVCR when 20 V transient tolerance or I2t fault logging is required; otherwise TPS25940ARVCR remains optimal for SATA SSD cost targets. |
| MP5418GD-Z | Monolithic 2.5–18 V eFuse with 45 mΩ RON, 0.5–6 A current limit, but no DevSleep mode or UL recognition. | Lacks SATA Device Sleep support and UL safety certification; suitable for consumer STB or DTV where low-IQ sleep is not mandated. | Choose MP5418GD-Z only for non-SATA, non-safety-critical applications; TPS25940ARVCR is mandatory for enterprise SSD qualification. |
Compared with TPS25942ARVCR and MP5418GD-Z, the TPS25940ARVCR uniquely balances SATA-compliant DevSleep IQ (95 µA), UL 2367/60950 certification, and 42 mΩ RON in a cost-optimized WQFN-20 package-making it the only qualified solution for PCIe/SATA SSD reference designs requiring JEDEC MO-269B compliance.
Availability
TPS25940ARVCR is available at Aetrix Electronics and suitable for PCIe/SATA SSDs, enterprise server holdup power systems, and adapter-powered storage enclosures requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for TPS25940ARVCR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader delivering analog, embedded processing, and connectivity solutions for industrial, automotive, and communications markets.
The TPS25940x product line was designed specifically for high-reliability storage power management-integrating reverse blocking, DevSleep, and safety certifications to replace discrete protection circuits in SSDs and RAID subsystems.
FAQ
What is the maximum input voltage rating for the TPS25940ARVCR?
The TPS25940ARVCR has an absolute maximum input voltage rating of 20 V for continuous operation and 22 V for 10-ms transients. Its recommended operating range is 2.7 V to 18 V, making it compatible with standard 3.3 V, 5 V, and 12 V DC rails used in SATA SSDs and server backplanes. Exceeding 18 V continuously may trigger overvoltage protection via the OVP pin or cause permanent damage.
Does the TPS25940ARVCR support true reverse current blocking, and how does it work?
Yes, the TPS25940ARVCR implements true reverse current blocking by continuously monitoring the voltage difference between IN and OUT pins. When V(IN) falls below V(OUT) − 9.3 mV (typical), the internal back-to-back FETs shut off within 1 µs, preventing backfeed from load-side holdup capacitors into a failed upstream supply. This function is intrinsic to the device architecture and requires no external components.
How is the current limit set on the TPS25940ARVCR, and what is its accuracy?
The current limit on the TPS25940ARVCR is set using an external resistor (RILIM) connected from the ILIM pin to GND. With RILIM = 16.9 kΩ, the device limits at 5.2 A (±8%); with RILIM = 150 kΩ, it limits at 0.58 A (±8%). The accuracy is maintained across temperature (−40°C to 125°C) and input voltage (2.7–18 V), as verified in TI's SLVSCF3A datasheet Section 7.5.
What is the purpose of the DEVSLP pin on the TPS25940ARVCR, and what happens in DevSleep mode?
On the TPS25940ARVCR, the DEVSLP pin is an active-high control input that enables SATA Device Sleep compliance. When driven high, the device enters DevSleep mode, reducing quiescent current to 95 µA typical while maintaining full fault detection (OVP, UVLO, thermal, reverse voltage) and retaining the programmed current limit (0.55–0.8 A). This mode is essential for meeting JEDEC MO-269B low-power idle requirements in SSDs.
Is the TPS25940ARVCR UL-recognized, and which standards apply?
Yes, the TPS25940ARVCR is UL-recognized under File No. 169910 for UL 2367 (Standard for Low-Voltage Fuses) and complies with UL60950-1 (Safety of Information Technology Equipment). These certifications validate its safe operation during single-point failures-including ILIM resistor open/short conditions-and confirm its suitability for use in enterprise storage and telecom infrastructure where regulatory compliance is mandatory.
TPS25940ARVCR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 20-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Electronic Fuse
- Sensing Method:
- -
- Accuracy:
- ±8%
- Voltage - Input:
- 2.7V ~ 18V
- Current - Output:
- 5.3A
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-WQFN (4x3)
TPS25940ARVCR FAQ
1.How can I place an order for TPS25940ARVCR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS25940ARVCR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS25940ARVCR reliable?
The price and inventory of TPS25940ARVCR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS25940ARVCR is usually 5 days.
3.What payment methods are accepted for TPS25940ARVCR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS25940ARVCR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS25940ARVCR?
TPS25940ARVCR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS25940ARVCR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS25940ARVCR?
For technical support, including TPS25940ARVCR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS25940ARVCR requirements.
6.How does Aetrix verify that TPS25940ARVCR is sourced from the original manufacturer or authorized distributors?
All TPS25940ARVCR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS25940ARVCR meets industry standards.
7.What is the process for return or replacement of TPS25940ARVCR?
All TPS25940ARVCR units undergo pre-shipment inspection (PSI). If there is an issue with TPS25940ARVCR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS25940ARVCR part is unused and in its original packaging.
Return procedure for TPS25940ARVCR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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