Texas Instruments TPS3106K33DBVR

Overview

TPS3106K33DBVR from Texas Instruments is an ultralow-quiescent-current voltage supervisor IC with dual monitoring capability-VDD and SENSE inputs-designed for power sequencing and reset assertion in low-power embedded systems. It features a fixed 2.941 V (±0.75%) VDD trip point, 1.2 μA typical supply current, 130 ms power-on reset delay, open-drain RSTVDD and RSTSENSE outputs, and operates across –40°C to 125°C. Used in battery-powered DSP/microcontroller systems requiring precise, low-power supply supervision.

For engineers reviewing the TPS3106K33DBVR datasheet, TPS3106K33DBVR pinout, TPS3106K33DBVR application, or TPS3106K33DBVR equivalent, this page delivers verified technical context, exact pin functions, real-world timing behavior, confirmed alternative parts, and design-meaningful specifications-not generic marketing claims.

Technical Context

The TPS3106K33DBVR implements independent dual-threshold supervision: VDD is monitored against a factory-trimmed 2.941 V (±0.75%) threshold with 50 mV hysteresis, while SENSE monitors external voltages against a fixed 0.551 V reference (±0.009 V at 25°C) with 15 mV hysteresis. Both paths drive dedicated open-drain outputs-RSTVDD and RSTSENSE-with propagation delays under 40 μs and a shared manual reset (MR) input with internal 100 kΩ pullup.

It operates from 0.9 V to 3.6 V supply, draws ≤3 μA over full temperature range when VDD > VIT–, asserts RESET below threshold with defined behavior down to 0.4 V VDD, and includes no watchdog or PFI/PFO circuitry-distinguishing it from TPS3103 and TPS3110 variants in the same family.

Key Specifications

Pinout & Package

TPS3106K33DBVR is housed in a 6-pin SOT-23 (DBV) package with exposed pad not electrically connected. The package is RoHS-compliant, moisture-sensitive level 1, and rated for reflow per JEDEC J-STD-020.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar voltage supervision applications.

Compared with TPS3106K33DBVR, TPS3106K33DBVT offers identical performance in a different packaging format, while TPS3808G33DBVR trades dual monitoring and ultra-low current for higher drive strength and simpler output topology-making it suitable only for single-supply applications where 1.3 μA extra quiescent draw is acceptable.

Availability

TPS3106K33DBVR is available at Aetrix Electronics and suitable for battery-powered microcontrollers, DSP power sequencing, industrial PLC I/O modules, and automotive body control units requiring stable component supply, long-term lifecycle support, and guaranteed traceability.

Supply support for TPS3106K33DBVR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of experience in high-reliability industrial and automotive ICs.

The TPS31xx family was designed specifically for low-power, precision voltage supervision in resource-constrained embedded systems-emphasizing nanoscale quiescent current, factory-trimmed thresholds, and dual-input flexibility without compromising temperature stability or ESD robustness.

FAQ

What is the exact VDD threshold voltage of the TPS3106K33DBVR and how does it vary with temperature?

The TPS3106K33DBVR has a nominal VDD threshold (VIT–) of 2.941 V at 25°C, with ±0.75% initial accuracy. Over –40°C to 125°C, the threshold ranges from 2.823 V to 3.058 V per datasheet Section 6.5. Its temperature coefficient is –0.012%/K to –0.019%/K, meaning drift is bounded and predictable-critical for designs operating across automotive or industrial temperature ranges. This value is factory-trimmed and does not require external calibration.

Can the TPS3106K33DBVR monitor a 1.6 V rail using the SENSE input, and what resistor values are needed?

Yes-the TPS3106K33DBVR SENSE input compares against a fixed 0.551 V reference. To monitor a 1.6 V rail, use a resistor divider where R1 connects to the 1.6 V source and R2 connects to GND, with SENSE tied to the R1–R2 node. Per Equation 1 in the datasheet, R1 ≈ R2 × (1.6 V / 0.551 V − 1) ≈ 1.9 × R2. For low current, select R2 = 430 kΩ and R1 = 820 kΩ-yielding ~1.2 μA divider current and maintaining accuracy within datasheet tolerance.

Does the TPS3106K33DBVR include a watchdog timer, and how does it differ from the TPS3110 series?

No, the TPS3106K33DBVR does not include a watchdog timer. It belongs to the TPS3106 subfamily, which provides dual open-drain reset outputs (RSTVDD and RSTSENSE) but no WDI input or watchdog logic. In contrast, the TPS3110 series integrates a watchdog timer with WDI input and push-pull RESET. Selecting TPS3106K33DBVR intentionally excludes watchdog functionality-ideal when only voltage supervision is required and board space or BOM count must be minimized.

What is the minimum VDD voltage at which the TPS3106K33DBVR can assert a valid RESET signal?

The TPS3106K33DBVR asserts RESET with defined behavior down to VDD = 0.4 V, as specified in Section 3 and Table 6.5 (VOL test condition). Below 0.4 V, the device ceases operation and outputs become indeterminate. This 0.4 V minimum enables reliable reset assertion during deep battery discharge or severe brownout-unlike many supervisors that require ≥0.8 V to function-making TPS3106K33DBVR especially suited for energy-harvesting and ultra-low-power applications.

How does the manual reset (MR) pin interact with the two reset outputs on the TPS3106K33DBVR?

The MR pin is a shared active-low input that forces both RSTVDD and RSTSENSE low simultaneously, regardless of VDD or SENSE voltage levels. When MR is pulled low, both outputs remain low for the full 130 ms reset timeout period-even if MR returns high before timeout completes. The internal 100 kΩ pullup allows MR to be left floating when unused, and no external debounce is required. This unified MR behavior ensures coordinated system-wide reset initiation across multiple power domains.