Texas Instruments TPS3125L30DBVRG4

Overview

TPS3125L30DBVRG4 from Texas Instruments is an ultralow-voltage processor supervisory IC with 2.64 V reset threshold, 180 ms power-on reset delay, manual reset (MR) input, and watchdog timer timeout of 0.8 s. It operates from 0.75 V to 3.3 V supply and delivers 14 µA typical supply current at 3.3 V. Used for reliable power sequencing and fault recovery in low-voltage DSPs and microcontrollers.

For engineers reviewing the TPS3125L30DBVRG4 datasheet, TPS3125L30DBVRG4 pinout, TPS3125L30DBVRG4 application, or TPS3125L30DBVRG4 equivalent, key selection criteria include reset threshold accuracy (±3% over temperature), SOT23-5 package compatibility, push-pull active-low RESET output, MR input logic level tolerance, and watchdog retrigger timing constraints.

Technical Context

The TPS3125L30DBVRG4 integrates a precision voltage reference, comparator, 180 ms internal reset timer, and watchdog timer with 0.8 s timeout. Its reset assertion occurs when VDD falls below 2.64 V (VIT−), with 30 mV hysteresis for noise immunity.

It features a manual reset input (MR) that forces active-low RESET regardless of VDD status, and supports watchdog retriggering via WDI transitions. The device uses internal pull-up on MR (27 kΩ) and provides push-pull RESET output capable of sinking 3 mA at 3.3 V with VOL ≤ 0.4 V.

Key Specifications

Pinout & Package

SOT23-5 package (DBV), 2.9 mm × 1.6 mm footprint, surface-mount, lead-free and RoHS-compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar processor supervisory applications.

Compared with TPS3125L30DBVRG4, the DBVT variant offers identical performance in a smaller reel format ideal for development, while TPS3808G30DBVR trades away MR and watchdog capability for delay flexibility-making it unsuitable as a drop-in replacement where system-level fault recovery is mandatory.

Availability

TPS3125L30DBVRG4 is available at Aetrix Electronics and suitable for battery-powered equipment, industrial microcontroller systems, and wireless communication baseband designs requiring stable component supply and long-term lifecycle support.

Supply support for TPS3125L30DBVRG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company delivering analog and embedded processing solutions, with leadership in power management, signal chain, and microcontrollers.

The TPS312x family was designed specifically for ultralow-voltage supervision of DSPs, microcontrollers, and microprocessors in portable, industrial, and communications equipment where supply margin is constrained and reset reliability is critical.

FAQ

What is the exact reset threshold voltage of the TPS3125L30DBVRG4?

The TPS3125L30DBVRG4 has a nominal reset threshold voltage (VIT−) of 2.64 V, with guaranteed range of 2.57 V to 2.71 V across −40°C to 85°C. This value is factory-trimmed and specified in Table 1 of the SLVS227B datasheet under "TPS3125L30" row. The "L30" suffix explicitly denotes the 3.0 V nominal supply version with −12% threshold offset (3.0 V × 0.88 = 2.64 V).

Does the TPS3125L30DBVRG4 support watchdog functionality?

Yes, the TPS3125L30DBVRG4 includes a watchdog timer with 0.8 s typical timeout (ttout). A rising or falling edge on the WDI pin resets the timer; failure to retrigger within ttout causes RESET to assert for 180 ms. This feature is confirmed in the Functional Block Diagram, Timing Diagrams, and Electrical Characteristics table of the TPS3125L30DBVRG4 datasheet.

What is the function of the MR pin on the TPS3125L30DBVRG4?

The MR (Manual Reset) pin on the TPS3125L30DBVRG4 is an active-low asynchronous input that forces the RESET output low regardless of VDD level or watchdog state. It features an internal 27 kΩ pull-up to VDD, so grounding MR via switch or GPIO initiates immediate system reset. This behavior is documented in the Function Tables and Timing Diagrams for TPS3123/5/6/8 devices.

Is the RESET output of the TPS3125L30DBVRG4 push-pull or open-drain?

The TPS3125L30DBVRG4 provides a push-pull, active-low RESET output. This is confirmed in Table 2 ("Reset Topology") of the datasheet, which lists "X" under PUSH-PULL for TPS3125. Unlike open-drain variants, it actively drives high when inactive, eliminating the need for an external pull-up resistor and simplifying interface with modern CMOS inputs.

What package type and footprint does the TPS3125L30DBVRG4 use?

The TPS3125L30DBVRG4 uses the SOT23-5 (DBV) package: a 5-pin, surface-mount, lead-free plastic package measuring 2.9 mm × 1.6 mm with 0.95 mm height and 0.95 mm pin pitch. Pin 1 is marked with a dot; top-view pinout is VDD–GND–RESET–WDI–MR. This is shown in Figure 1 ("DBV PACKAGE (TOP VIEW)") and confirmed in the Package Information section of the datasheet.