Texas Instruments TPS3307-25DR
- Part No.:
- TPS3307-25DR
- Manufacturer:
- Texas Instruments
- Category:
- Supervisors
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
TPS3307-25DR.pdf
- Description:
- IC SUPERVISOR 3 CHANNEL 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:2,284
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TPS3307-25DR from Texas Instruments is a triple-voltage supervisor IC designed for DSP and microprocessor-based systems requiring independent monitoring of 3.3V, 2.5V, and adjustable supply rails. It delivers fixed 200ms power-on reset delay, operates from 2V to 6V supply, draws ≤40µA quiescent current, and features dual active-low/high RESET outputs. It is used in industrial programmable controllers and automotive ECUs where reliable multi-rail power sequencing is critical.
For engineers reviewing the TPS3307-25DR datasheet, TPS3307-25DR pinout, TPS3307-25DR application, or TPS3307-25DR equivalent, key selection criteria include SENSE1/SENSE2 threshold voltages (2.93V/2.25V), manual reset (MR) timing behavior, SOIC-8 package compatibility, and guaranteed RESET assertion down to VDD ≥1.1V - all essential for robust system initialization in battery-powered and embedded control designs.
Technical Context
The TPS3307-25DR implements three independent voltage comparators with temperature-compensated 1.25V internal reference, enabling precise monitoring of nominal 3.3V (SENSE1), 2.5V (SENSE2), and user-defined >1.25V (SENSE3) supplies. Each input includes hysteresis (20–40mV depending on threshold) to prevent noise-induced false resets.
Its internal 200ms reset timer initiates only after all three SENSE inputs exceed their respective VIT+ thresholds; RESET remains asserted if any SENSE drops below VIT−. The MR input provides asynchronous reset override, while dual complementary RESET outputs support both active-low and active-high logic interface requirements without external inversion.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply voltage range | 2V to 6V - supports wide-input industrial and automotive power rails without external regulation. |
| SENSE1 threshold (VIT+) | 2.93V (typ) - precisely monitors standard 3.3V supply with ±3% tolerance over temperature. |
| SENSE2 threshold (VIT+) | 2.25V (typ) - targets 2.5V rail with built-in margin for stable detection under load transients. |
| Reset delay time | 200ms (typ) - ensures complete processor core and peripheral initialization before release; no external capacitor required. |
| Quiescent supply current | 40µA (max) - enables long-term operation in battery-backed or energy-constrained systems. |
| Operating temperature | –40°C to +85°C - qualified for industrial and automotive under-hood environments. |
| RESET assertion threshold | VDD ≥1.1V - guarantees valid reset signal generation even during brownout conditions. |
Pinout & Package
TPS3307-25DR is packaged in an 8-pin SOIC (D) package, 3.9mm × 4.9mm body, 1.75mm max height, with standard 1.27mm pitch and RoHS-compliant NiPdAu lead finish. Pin 1 is located at the top-left corner with a molded index notch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - SENSE1 | Input | Monitors primary 3.3V rail; asserts RESET if voltage falls below 2.93V (VIT+). |
| 2 - SENSE2 | Input | Monitors secondary 2.5V rail; asserts RESET if voltage falls below 2.25V (VIT+). |
| 3 - SENSE3 | Input | Adjustable input for third rail (>1.25V); threshold set by external resistor divider referencing 1.25V internal reference. |
| 4 - GND | Power | Analog and digital ground reference; must be low-impedance connection to minimize noise coupling into comparators. |
| 5 - RESET | Output | Active-low open-drain output; requires external pull-up for logic-level compatibility with host processor. |
| 6 - RESET | Output | Active-high push-pull output; directly interfaces with logic inputs needing high-true reset signaling. |
| 7 - MR | Input | Manual reset input; low pulse ≥100ns forces immediate RESET assertion regardless of SENSE states. |
| 8 - VDD | Power | Main supply input (2–6V); powers internal reference, comparators, and output drivers; bypass capacitor mandatory. |
Key Features
| Feature | Design Value |
|---|---|
| Triple independent voltage monitoring | Simultaneously supervises 3.3V, 2.5V, and user-defined rail - eliminates need for multiple discrete supervisors in multi-supply systems. |
| Fixed 200ms reset timeout | Guaranteed delay without external timing components - reduces BOM count and layout area while ensuring deterministic boot timing. |
| Dual complementary RESET outputs | Provides both active-low and active-high signals - simplifies interface to diverse host processors (e.g., MSP430, C2000, ARM Cortex-M) without level-shifting or inverters. |
| Temperature-compensated 1.25V reference | Enables stable SENSE3 threshold across –40°C to +85°C - critical for accuracy in unregulated or thermally varying environments. |
| Ultra-low 40µA supply current | Minimizes standby power draw - suitable for always-on monitoring in portable, IoT, and battery-operated equipment. |
Applications
| Industrial Programmable Logic Controllers | Automotive Engine Control Units |
|---|---|
|
Use Scenario: Monitors 3.3V I/O, 2.5V ADC reference, and 5V sensor supply in PLC backplane modules during cold start and voltage sag events. IC Role / Device Role / Timing Role: Triple supervisor ensures synchronized reset release only after all rails stabilize above thresholds, preventing partial initialization faults. Use Value: Eliminates firmware-level watchdog fallbacks by guaranteeing hardware-enforced power-good sequencing per IEC 61131-2. |
Use Scenario: Supervises 3.3V MCU core, 2.5V CAN transceiver, and 12V-regulated 5V sensor bus in engine ECU under cranking (6.5V min) and load dump (40V transient) conditions. IC Role / Device Role / Timing Role: MR input accepts ignition switch signal to force reset on key-on; SENSE3 configured via divider for 5V rail monitoring. Use Value: Prevents ECU lockup during battery voltage fluctuations - meets ISO 16750-2 pulse 4 (cranking) and pulse 5a (load dump) immunity requirements. |
| Portable Medical Instrumentation | Wireless Baseband Processors |
|
Use Scenario: Ensures reliable startup of 3.3V RF front-end, 2.5V analog front-end, and 1.8V FPGA configuration rail in handheld ultrasound devices powered by Li-ion batteries. IC Role / Device Role / Timing Role: Low 40µA IDD extends battery life in sleep mode; RESET outputs coordinate wake-up sequence across subsystems. Use Value: Enables >100-hour standby with guaranteed reset integrity - satisfies IEC 62304 Class B software safety requirements. |
Use Scenario: Validates 3.3V baseband ASIC, 2.5V memory interface, and 1.2V core supply in LTE/5G small cell radios during thermal cycling and hot-swap events. IC Role / Device Role / Timing Role: Dual RESET outputs drive separate reset domains for modem and application processor; hysteresis prevents chatter near threshold. Use Value: Reduces field failure rate due to marginal power conditions - achieves <1 FIT failure rate in carrier-grade deployments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar triple-voltage supervisor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS3307-25DGN | HVSSOP-8 (3mm × 3mm) vs SOIC-8; identical electrical specs and pinout; 30% smaller footprint. | Suitable for space-constrained PCBs; requires modified land pattern and stencil design per TI DGN0008D spec. | Select when board area is critical and thermal performance allows lower power dissipation (1.37W vs 0.464W). |
| MAX6816EPA+ | Single 3.3V supervisor (not triple); 5ms reset delay; higher 100µA supply current; DIP-8 package. | Limited to single-rail monitoring; lacks SENSE2/SENSE3 inputs and dual RESET outputs. | Only viable for legacy DIP-based designs where triple supervision is unnecessary and 200ms delay is not required. |
Compared with TPS3307-25DGN, the TPS3307-25DR offers identical functionality in a larger but more manufacturable SOIC package with broader reflow compatibility; versus MAX6816EPA+, it provides full triple-rail supervision, longer reset timing, and lower power - making it the only direct functional alternative for modern multi-supply embedded systems.
Availability
TPS3307-25DR is available at Aetrix Electronics and suitable for industrial programmable controls, automotive electronic control units, and portable medical instrumentation requiring stable component supply across extended product lifecycles.
Supply support for TPS3307-25DR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of experience in high-reliability industrial and automotive ICs.
The TPS3307 family was engineered specifically for DSP and microprocessor-based systems demanding simultaneous multi-rail power supervision - addressing the need for deterministic reset sequencing in complex embedded platforms.
FAQ
What is the exact SENSE1 and SENSE2 threshold voltage for TPS3307-25DR?
The TPS3307-25DR has a typical SENSE1 threshold (VIT+) of 2.93V and SENSE2 threshold (VIT+) of 2.25V, with ±3% variation over temperature and supply voltage. These values are factory-trimmed and specified in the Electrical Characteristics table of the SLVS199C datasheet. The TPS3307-25DR uses these fixed thresholds to monitor standard 3.3V and 2.5V rails without external resistor networks.
Does TPS3307-25DR require an external capacitor for the reset delay function?
No, the TPS3307-25DR integrates a precision 200ms reset timer that requires no external capacitor. This internal timing circuit eliminates component count and layout sensitivity associated with RC-based delays. The TPS3307-25DR guarantees this delay starts only after all three SENSE inputs exceed their VIT+ thresholds, ensuring synchronized system initialization.
Can TPS3307-25DR monitor a 5V supply rail?
Yes - the TPS3307-25DR's SENSE3 input is adjustable and can monitor any supply >1.25V using an external resistor divider referenced to its internal 1.25V bandgap. For a 5V rail, a standard 2.87kΩ/1kΩ divider yields ~1.25V at SENSE3, enabling accurate detection. The TPS3307-25DR does not natively monitor 5V on SENSE1 or SENSE2, which are fixed at 2.93V and 2.25V respectively.
What is the minimum VDD required for TPS3307-25DR to assert RESET?
The TPS3307-25DR asserts RESET when VDD rises to ≥1.1V, as specified in the "Power-up reset voltage" parameter. This ensures early reset assertion during power ramp-up, even before the monitored SENSE rails reach their thresholds. The TPS3307-25DR maintains valid RESET output down to this level, supporting robust brownout detection in low-voltage systems.
Is TPS3307-25DR pin-compatible with other members of the TPS3307 family?
Yes - all TPS3307-x variants (including TPS3307-18DR, TPS3307-25DR, and TPS3307-33DR) share identical SOIC-8 pinout, electrical interface, and timing behavior. Only the SENSE1/SENSE2 threshold voltages differ between part numbers. The TPS3307-25DR can be substituted in designs originally using TPS3307-18DR or TPS3307-33DR with no PCB changes, provided the monitored rail voltages match its 2.93V/2.25V thresholds.
TPS3307-25DR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Multi-Voltage Supervisor
- Number of Voltages Monitored:
- 3
- Voltage - Threshold:
- 2.25V, 2.93V, Adj
- Output:
- Push-Pull, Totem Pole
- Reset:
- Active High/Active Low
- Reset Timeout:
- 140ms Minimum
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
TPS3307-25DR FAQ
1.How can I place an order for TPS3307-25DR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS3307-25DR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS3307-25DR reliable?
The price and inventory of TPS3307-25DR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS3307-25DR is usually 5 days.
3.What payment methods are accepted for TPS3307-25DR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS3307-25DR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS3307-25DR?
TPS3307-25DR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS3307-25DR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS3307-25DR?
For technical support, including TPS3307-25DR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS3307-25DR requirements.
6.How does Aetrix verify that TPS3307-25DR is sourced from the original manufacturer or authorized distributors?
All TPS3307-25DR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS3307-25DR meets industry standards.
7.What is the process for return or replacement of TPS3307-25DR?
All TPS3307-25DR units undergo pre-shipment inspection (PSI). If there is an issue with TPS3307-25DR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS3307-25DR part is unused and in its original packaging.
Return procedure for TPS3307-25DR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TPS3307-25DR Tags

-
MIC826SYMT-TR
Microchip Technology

-
APX803S-31SA-7
Diodes Incorporated

-
APX803L20-29SA-7
Diodes Incorporated
-
TPS3828-33DBVR
Texas Instruments

-
V6340RSP3B+
EM Microelectronic

-
EM6325CXSP5B-2.9+
EM Microelectronic

-
MCP120T-300I/TT
Microchip Technology

-
MCP130T-315I/TT
Microchip Technology

-
MCP120T-475I/TT
Microchip Technology

-
MCP111T-300E/TT
Microchip Technology

-
MCP120T-315I/TT
Microchip Technology

-
MCP809T-315I/TT
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

