Texas Instruments TPS3510D

Overview

TPS3510D from Texas Instruments is a dedicated power-supply supervisor IC for PC ATX and industrial switching power supplies, providing overvoltage (12 V/5 V/3.3 V), undervoltage (5 V/3.3 V), fault latching, open-drain PGO and FPO outputs, and 300-ms power-good delay. It operates from 4 V to 15 V supply and supports –40°C to 85°C ambient.

For engineers reviewing the TPS3510D datasheet, TPS3510D pinout, TPS3510D application, or TPS3510D equivalent, this page delivers verified functional roles, timing-critical parameters (75-ms UVP enable delay, 2.3-ms PSON-to-FPO turnoff delay, 73-µs noise deglitch), package-specific thermal ratings, and validated alternatives for ATX PSU supervisory design.

Technical Context

The TPS3510D implements independent comparator-based monitoring of VS33 (3.3 V), VS5 (5 V), and VDD (12 V via supply rail) with 73-µs noise filtering per channel. Its internal latch holds FPO high on OV/UV fault until PSON toggles low→high, while PGO asserts high only after all monitored rails exceed thresholds and the 300-ms delay expires.

It integrates a 38-ms PSON input debounce block, disables UVP for 75 ms after PSON assertion to prevent false turn-on lockout, and features separate 150-µs debounced response paths for PGI-driven PGO deassertion versus rail-driven fault detection - ensuring robust sequencing in multi-rail ATX systems.

Key Specifications

Pinout & Package

TPS3510D is housed in an 8-pin SOIC (D) package (JEDEC MS-012AA), 3.9 mm wide × 4.9 mm long × 1.75 mm max height, with NIPDAU lead finish and MSL Level-1 rating.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar power-supply supervision applications.

Compared with TPS3510D, TPS3511DR offers faster power-good response but sacrifices ATX-standard 300-ms delay compliance; TLV809E33DBZR reduces functionality to basic reset generation, eliminating critical features like multi-rail coordination, fault latching, and PSON-controlled reset - making it unsuitable as a drop-in replacement.

Availability

TPS3510D is available at Aetrix Electronics and suitable for ATX power supply design, industrial PLC power sequencing, and medical device power integrity validation requiring stable component supply, long-term lifecycle support, and RoHS-compliant sourcing.

Supply support for TPS3510D includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in power-supply control ICs.

The TPS3510D belongs to TI's power-supply supervisor product line, engineered specifically for ATX and industrial switching power supplies requiring coordinated multi-rail monitoring, fault latching, and strict timing compliance.

FAQ

What is the exact power-good delay timing of the TPS3510D?

The TPS3510D provides a fixed 300-ms power-good delay (td1) from PGI/VS33/VS5 stabilization to PGO assertion. This value is specified in the Electrical Characteristics table (typical 300 ms, min 200 ms, max 450 ms at VDD = 5 V) and distinguishes it from the TPS3511 family's 150-ms delay. The TPS3510D's 300-ms delay ensures full compliance with ATX specification requirements for system boot sequencing.

Does the TPS3510D support 12 V overvoltage detection without external components?

Yes, the TPS3510D supports 12 V overvoltage detection natively through its VDD pin - no external resistor divider is needed. When VDD is connected directly to the 12 V rail, the internal comparator monitors for voltages exceeding 13.8 V (typical), with 73-µs noise deglitching. This capability is explicitly confirmed in the Functional Block Diagram and Electrical Characteristics section of the SLVS312A datasheet for the TPS3510D.

How does the TPS3510D handle short-circuit conditions during power-up?

The TPS3510D incorporates a 75-ms undervoltage protection (UVP) enable delay after PSON is asserted low. This prevents false UVP triggering during the initial 3.3 V and 5 V rail ramp-up phase when output capacitors are charging - a common scenario during short-circuit turn-on testing. The delay is implemented in hardware and is independent of external components, ensuring robust immunity without design overhead.

What are the absolute maximum ratings for the TPS3510D's FPO and PGO pins?

The TPS3510D's FPO pin tolerates up to 16 V (open-drain output), while the PGO pin is rated for a maximum of 8 V. Both outputs are designed for open-drain operation and require external pull-up resistors - typically to 5 V or 12 V for FPO (to drive main rail enable logic) and to 3.3 V or 5 V for PGO (to interface with motherboard reset controllers). These ratings are specified in the Absolute Maximum Ratings table of the SLVS312A datasheet.

Is the TPS3510D pin-compatible with the TPS3511DR?

Yes, the TPS3510D and TPS3511DR share identical SOIC-8 (D) packaging, pinout, and electrical interface - including matching VDD, VS33, VS5, PGI, PGO, FPO, PSON, and GND assignments. However, they differ in power-good delay (300 ms vs. 150 ms) and operating temperature range (–40°C to 85°C vs. –40°C to 125°C). While pinout-compatible, substitution requires verification of timing and thermal requirements in the target application.