Texas Instruments TPS3510DG4

Overview

TPS3510DG4 from Texas Instruments is a power supply supervisor IC for PC ATX and industrial switching power supplies, providing overvoltage (12 V/5 V/3.3 V), undervoltage (5 V/3.3 V), fault protection (FPO), open-drain power good output (PGO), and PSON control with 300-ms PGI-to-PGO delay. It operates from 4 V to 15 V and supports –40°C to 85°C ambient.

For engineers reviewing the TPS3510DG4 datasheet, TPS3510DG4 pinout, TPS3510DG4 application, or TPS3510DG4 equivalent, key selection considerations include its 75-ms short-circuit turnon protection, 73-µs OVP noise deglitching, 2.3-ms PSON-to-FPO turnoff delay, and SOIC-8 package compatibility with legacy motherboard designs.

Technical Context

The TPS3510DG4 integrates independent comparators for 12 V (via VDD), 5 V (VS5), and 3.3 V (VS33) overvoltage detection, plus dual thresholds (0.95 V and 1.15 V) on PGI for power-good validation. Its latch-based fault architecture holds FPO high until PSON toggles low→high, enabling manual reset of overvoltage/undervoltage faults.

It implements three critical timing functions: 300-ms power-good assertion delay after valid PGI/VS5/VS33 rise, 75-ms UVP enable delay post-PSON low, and 38-ms PSON input debounce - all with 73-µs noise filtering on OVP inputs to prevent false triggering from transient spikes.

Key Specifications

Pinout & Package

TPS3510DG4 is housed in an 8-pin SOIC (D) package, 3.9 mm wide, 4.9 mm long, 1.75 mm max height, RoHS-compliant with NIPDAU lead finish and JEDEC MS-012 AA outline.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar power-supply supervisor applications.

Compared with TPS3510DG4, TPS3511DR offers faster power-good response but sacrifices ATX-standard 300-ms delay compliance, while TPS3823-33DBVR reduces integration at the cost of losing 5 V/12 V monitoring, PSON interface, and fault latching - making TPS3510DG4 the only option for complete ATX-compliant supervision in SOIC-8.

Availability

TPS3510DG4 is available at Aetrix Electronics and suitable for desktop PC power supplies, industrial ATX-compatible PSUs, server backplane power management, and embedded computing power sequencing requiring stable component supply and long-term lifecycle support.

Supply support for TPS3510DG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of experience in power supply control ICs.

The TPS3510DG4 belongs to TI's power-supply supervisor product line, designed specifically for ATX and industrial switching power supplies requiring integrated overvoltage, undervoltage, fault latching, and power-good sequencing functions.

FAQ

What is the power-good delay of the TPS3510DG4, and how is it configured?

The TPS3510DG4 has a fixed 300-ms power-good delay from PGI/VS5/VS33 valid assertion to PGO high transition. This delay is inherent to the TPS3510 variant and is not user-configurable - it is implemented via an internal timer and matches ATX specification requirements. No external components are needed to set or adjust this timing.

Does the TPS3510DG4 support 12 V overvoltage protection without external resistors?

Yes, the TPS3510DG4 supports 12 V overvoltage protection directly through its VDD pin, which serves a dual role as both supply input and 12 V sense node. The internal 13.8 V OVP threshold eliminates the need for external resistor dividers, simplifying design and improving accuracy compared to solutions requiring precision external networks.

How does the TPS3510DG4 handle short-circuit conditions during power-up?

The TPS3510DG4 incorporates a 75-ms undervoltage protection enable delay after PSON goes low. This prevents false UVP latching during initial inrush when 3.3 V and 5 V rails are still ramping - a common cause of turnon failure in PSUs with large bulk capacitors. The delay ensures stable rail voltages before UVP monitoring activates.

What is the function of the PSON pin on the TPS3510DG4, and what timing behavior does it exhibit?

The PSON pin on the TPS3510DG4 is an active-low power supply enable input. It features 38-ms hardware debounce to reject noise, and a 2.3-ms delay from PSON deassertion to FPO deactivation - ensuring controlled main rail shutdown. Toggling PSON low→high resets the fault latch, allowing recovery from OVP/UVP events without cycling input power.

Can the TPS3510DG4 monitor both 3.3 V and 5 V rails simultaneously, and what are their respective thresholds?

Yes, the TPS3510DG4 monitors both rails independently: VS33 accepts the 3.3 V rail with 2.2 V typ undervoltage and 3.9 V typ overvoltage thresholds; VS5 accepts the 5 V rail with 3.5 V typ undervoltage and 6.1 V typ overvoltage thresholds. These values are factory-trimmed and specified over –40°C to 85°C, ensuring reliable detection across operating conditions.