Texas Instruments TPS3510DRG4

Overview

TPS3510DRG4 from Texas Instruments is a dedicated power-supply supervisor IC for PC ATX and industrial switching power supplies, providing overvoltage (12 V/5 V/3.3 V), undervoltage (5 V/3.3 V), fault protection (FPO), open-drain power-good output (PGO), and PSON-controlled reset logic. It operates from 4 V to 15 V supply and supports –40°C to 85°C ambient temperature.

For engineers reviewing the TPS3510DRG4 datasheet, TPS3510DRG4 pinout, TPS3510DRG4 application, or TPS3510DRG4 equivalent, this page delivers verified functional identity, validated timing behavior (300-ms PGI-to-PGO delay), confirmed dual-rail UV/OV thresholds, and precise SOIC-8 terminal mapping - all critical for ATX compliance, safety-critical PSU validation, and motherboard-level power sequencing design.

Technical Context

The TPS3510DRG4 implements independent comparator-based monitoring with 73-µs noise deglitching on all OV inputs (VS33, VS5, VDD) and 146-µs deglitching on UV inputs (VS33, VS5). Its internal state machine latches FPO high upon fault detection and requires PSON low-to-high transition to clear the latch.

It integrates a 300-ms programmable power-good delay (TPS3510 variant), 75-ms short-circuit turn-on protection after PSON assertion, 38-ms PSON debounce, and 2.3-ms PSON-to-FPO turnoff delay. All outputs (FPO, PGO) are open-drain with 20 mA sink capability (FPO) and 10 mA (PGO), compatible with 5 V–15 V pull-up voltages.

Key Specifications

Pinout & Package

TPS3510DRG4 is housed in an 8-pin SOIC (D) package per JEDEC MS-012AA, 1.75 mm max height, with gull-wing leads and RoHS-compliant NiPdAu finish. Pin 1 is located at top-left corner with beveled edge marking.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar power-supply supervision applications.

Compared with TPS3510DRG4, TPS3511DR offers faster power-good response but sacrifices ATX-compliant delay timing, while TL331IDR lacks integrated supervision logic entirely - requiring significant external components to replicate even basic UV/OV detection and latching.

Availability

TPS3510DRG4 is available at Aetrix Electronics and suitable for ATX power supply manufacturing, industrial DC-DC module production, and embedded computing platform development requiring stable component supply, long-lifecycle support, and RoHS-compliant sourcing.

Supply support for TPS3510DRG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in power-supply control ICs and system-level reliability engineering.

The TPS3510DRG4 belongs to TI's legacy power-supply supervisor family designed specifically for PC ATX and industrial switching power supplies - emphasizing robust fault detection, latch-and-reset behavior, and strict compliance with industry timing standards.

FAQ

What is the power-good delay of the TPS3510DRG4?

The TPS3510DRG4 provides a fixed 300-ms delay from valid PGI/VS33/VS5 input stabilization to high assertion of the open-drain PGO output. This delay is inherent to the TPS3510 variant and cannot be adjusted externally. The TPS3510DRG4 does not support programmable delay; its timing matches ATX12V 2.0+ specifications for safe motherboard boot sequencing.

Does the TPS3510DRG4 monitor the 12 V rail directly?

Yes - the TPS3510DRG4 monitors the 12 V rail indirectly through the VDD pin. When VDD exceeds 13.8 V (typical OVP threshold), the device asserts FPO high and pulls PGO low within 73 µs. This eliminates need for a separate 12 V sense resistor divider, simplifying layout and reducing component count in ATX PSUs.

How does the TPS3510DRG4 handle short-circuit conditions during power-on?

The TPS3510DRG4 incorporates a 75-ms delay after PSON is asserted low before enabling undervoltage protection on VS33 and VS5. This prevents false triggering during normal inrush current or brief output sag during capacitor charging. If a short persists beyond 75 ms, UV detection activates and latches FPO high.

Can the TPS3510DRG4 be used with a 3.3 V-only supply?

No - the TPS3510DRG4 requires a minimum 4 V supply on VDD to operate. While it monitors 3.3 V (VS33) and 5 V (VS5) rails, its own supply must be ≥4 V. For 3.3 V systems, a level-shifter or LDO is required to generate ≥4 V for VDD, or a different supervisor such as TPS3839 should be selected.

What is the maximum sink current capability of the TPS3510DRG4's FPO and PGO outputs?

The FPO output sinks up to 20 mA at 0.7 V (VDD = 5 V), while PGO sinks up to 10 mA at 0.4 V (VDD = 4 V). Both are open-drain and require external pull-up resistors. These ratings allow direct driving of optocouplers (e.g., PC817), logic gates, or microcontroller interrupt inputs without buffering.