My Inquiry
My Account
Texas Instruments TPS3613-01DGSR
- Part No.:
- TPS3613-01DGSR
- Manufacturer:
- Texas Instruments
- Category:
- Supervisors
- Package:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
TPS3613-01DGSR.pdf
- Description:
- IC SUPERVISOR 1 CHANNEL 10VSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:14,818
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TPS3613-01DGSR from Texas Instruments is a precision battery switchover supervisory IC with dual reset outputs (active-high and active-low), 100-ms power-on reset delay, adjustable supply voltage supervision via external resistors, and chip-enable signal gating with ≤3 ns propagation delay at 5 V. It delivers 40 µA max supply current and supports backup-battery operation up to 5.5 V while enabling data retention in CMOS RAM during brownout or main power failure - used in portable long-time monitoring equipment and advanced voice mail systems.
For engineers reviewing the TPS3613-01DGSR datasheet, TPS3613-01DGSR pinout, TPS3613-01DGSR application, or TPS3613-01DGSR equivalent, key selection considerations include its dual-reset architecture, VDD/VBAT switchover logic with 15-Ω VBAT-to-VOUT switch, 1.15 V nominal sense threshold with 12 mV hysteresis, 10-pin MSOP (VSSOP-DGS) package, and support for manual reset assertion with <1 µs response time.
Technical Context
The TPS3613-01DGSR integrates a precision voltage supervisor, power-on reset timer, dual-output reset generator, and bidirectional chip-enable gate. Its SENSE input monitors VDD through an external resistor divider to set the adjustable reset threshold (VIT = 1.15 V ±20 mV), while internal reference and comparator circuitry ensure stable triggering across −40°C to +85°C.
It implements intelligent backup-battery management: when VDD falls below VIT, the device disconnects VDD from VOUT and connects VBAT to VOUT via a 15-Ω NMOS switch - only if VBAT > VDD - preserving RAM power without reverse current flow. CEIN-to-CEOUT gating remains enabled during normal operation but disables within 15 µs of reset assertion to prevent bus corruption.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Current (IDD) | 40 µA max - enables ultra-low-power operation in battery-backed systems without compromising supervision accuracy. |
| Battery Supply Current (IBAT) | 100 nA max - minimizes drain on backup lithium cells during extended standby, extending system uptime. |
| Reset Delay Time | Fixed 100 ms - ensures reliable processor initialization after power stabilization, meeting standard boot timing requirements. |
| VIT Threshold Voltage | 1.13–1.17 V - precise, temperature-stable trip point for VDD supervision, with 12 mV hysteresis to prevent chatter near threshold. |
| CE Propagation Delay | ≤3 ns at VDD = 5 V - preserves high-speed memory access timing integrity during normal operation while blocking glitches during reset. |
| VDD-to-VOUT RDS(on) | 0.6–1 Ω - low-loss main supply path ensures minimal voltage drop (<200 mV at 200 mA), critical for low-voltage microcontroller rails. |
| VBAT-to-VOUT RDS(on) | 8–15 Ω - optimized for backup-current levels (≤7.5 mA), balancing low dropout with safe current limiting during switchover. |
Pinout & Package
TPS3613-01DGSR is housed in a 10-pin VSSOP (DGS) package - 3.0 mm × 3.0 mm footprint, 1.1 mm max height, MS-012 variant per JEDEC MO-187 - suitable for space-constrained portable designs and compatible with standard surface-mount reflow profiles (MSL Level-1).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VOUT (Pin 1) | Power output rail | Switched output connected to VDD or VBAT depending on switchover state; drives CMOS RAM VCC directly with ≤200 mV dropout. |
| VDD (Pin 2) | Main supply input | Primary power source (1.65–5.5 V); powers internal circuitry and supplies VOUT when active; monitored via SENSE feedback. |
| GND (Pin 3) | Ground reference | Common return path for all analog and digital functions; must be low-impedance to maintain reset threshold stability. |
| MR (Pin 4) | Manual reset input | Active-low asynchronous reset trigger; asserts RESET/RESET within 1 µs when pulled low, independent of VDD level. |
| CEIN (Pin 5) | Chip-enable input | Accepts processor CE signal; gated internally and passed to CEOUT only when reset is inactive - prevents memory write errors. |
| CEOUT (Pin 6) | Chip-enable output | Controlled CE signal delivered to RAM; pulled high to VOUT in disable mode, ensuring memory remains deselected during reset. |
| RESET (Pin 7) | Active-high reset output | Drives microcontroller reset pin high during fault condition; VOH ≥ VDD − 0.4 V at 3 mA load ensures TTL/CMOS compatibility. |
| SENSE (Pin 8) | Adjustable threshold input | High-impedance (±25 nA) node for external resistor divider; sets VIT by scaling VDD; bypass capacitor required for noise immunity. |
| RESET (Pin 9) | Active-low reset output | Complementary to RESET; sinks up to 3 mA; VOL ≤ 0.4 V guarantees clean logic-low assertion for processors requiring inverted reset. |
| VBAT (Pin 10) | Backup battery input | Accepts 1.5–5.5 V backup source; isolated from VOUT until VDD fails and VBAT > VDD - prevents backfeed and enables seamless switchover. |
Key Features
| Feature | Design Value |
|---|---|
| Dual active reset outputs | Simultaneous RESET (active-high) and RESET (active-low) eliminate need for external inverters in mixed-logic systems. |
| Adjustable VDD supervision | SENSE pin accepts resistor-divider configuration to set custom reset thresholds from 1.1 V upward - supports diverse supply rails. |
| Intelligent VDD/VBAT switchover | Automatic transition to backup power only when VDD < VIT and VBAT > VDD, with 55 mV VBSW hysteresis to prevent oscillation during recovery. |
| Sub-µA battery leakage | 100 nA max IBAT ensures multi-year shelf life for lithium coin-cell backups in unattended monitoring devices. |
| Chip-enable signal gating | CEIN-to-CEOUT path disabled within 15 µs of reset assertion, blocking erroneous memory writes while allowing final cycle completion. |
Applications
| Portable Battery-Powered Equipment | Advanced Voice Mail Systems |
|---|---|
Use Scenario: Handheld data loggers operating on primary Li-ion with coin-cell backup for RAM retention during recharge cycles. IC Role / Device Role / Timing Role: Supervisory controller managing VDD/VBAT switchover, asserting dual reset signals during brownout, and gating CE to prevent memory corruption. Use Value: Enables 10+ year data retention without external supervision circuitry; 40 µA IDD extends primary battery life; 100 nA IBAT preserves backup cell capacity. |
Use Scenario: Carrier-grade voice mail platforms requiring nonvolatile RAM preservation across AC power interruptions and scheduled maintenance outages. IC Role / Device Role / Timing Role: System-level power monitor providing 100-ms POR delay, manual reset capability, and CE gating synchronized to DSP reset sequence. Use Value: Eliminates need for discrete reset IC + analog switch + voltage detector; reduces BOM count by 3 components; ensures deterministic boot after grid failure. |
| Point-of-Sale Equipment | Automotive Systems |
Use Scenario: Retail POS terminals using SRAM-based transaction buffers that must retain unsynced sales data during brief utility dips or battery swaps. IC Role / Device Role / Timing Role: Real-time supply supervisor asserting RESET/RESET and isolating memory CE during voltage sag below 1.15 V. Use Value: Guarantees zero data loss during sub-100-ms sags; 1.1 V power-up threshold supports low-voltage microcontrollers; VSSOP package fits compact PCB layouts. |
Use Scenario: Telematics control units retaining GPS session state and diagnostic logs during engine cranking-induced voltage drops (down to 6 V). IC Role / Device Role / Timing Role: Automotive-qualified supervisor monitoring 12 V rail (via resistor divider), generating clean reset pulses, and enabling fail-safe memory holdover. Use Value: −40°C to +85°C operation meets AEC-Q100 ambient requirements; 7 V absolute max rating accommodates load-dump transients; dual reset outputs interface directly with MCU and FPGA. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar supervisory and battery switchover applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS3619-01DGSR | Fixed 3.08 V reset threshold; no adjustable SENSE input; identical VSSOP-10 package and CE gating functionality. | Suitable for systems with fixed 3.3 V supply rails where resistor-divider design overhead is undesirable. | Select when threshold is known and stable; avoids external resistor selection but lacks flexibility for multi-rail or low-voltage designs. |
| MAX6361KA29+T | 2.93 V fixed threshold; 12 µA supply current; no CE gating; single active-low reset output; 8-pin SOT23 package. | Targeted at cost-sensitive, space-constrained applications needing basic reset only - no battery switchover or memory protection. | Choose for simple POR-only use cases; not suitable for RAM backup or CE-controlled memory systems due to missing features. |
Compared with TPS3613-01DGSR, TPS3619-01DGSR trades adjustability for guaranteed 3.08 V accuracy and lower quiescent current, while MAX6361KA29+T offers minimal footprint and cost at the expense of switchover logic, dual reset, and CE control - making TPS3613-01DGSR uniquely suited for battery-backed memory integrity in variable-supply environments.
Availability
TPS3613-01DGSR is available at Aetrix Electronics and suitable for portable battery-powered equipment, advanced voice mail systems, point-of-sale terminals, automotive telematics, and portable long-time monitoring equipment requiring stable component supply across extended product lifecycles.
Supply support for TPS3613-01DGSR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-reliability supervisory and power-integrity solutions.
The TPS361x family was designed specifically for systems requiring robust, low-power supervision with integrated battery switchover and memory protection - targeting portable, industrial, and automotive applications demanding data retention during power disruption.
FAQ
What is the minimum supply voltage required for TPS3613-01DGSR to assert reset?
The TPS3613-01DGSR asserts reset when either VDD or VBAT rises above 1.1 V - this is the power-up reset voltage threshold specified in the datasheet. Below this level, both RESET and RESET remain asserted. The device remains functional down to 1.65 V for normal supervision, but the 1.1 V threshold ensures early detection of marginal supply conditions before system instability occurs. This behavior is confirmed in the Electrical Characteristics table under "Power-up reset voltage".
How does TPS3613-01DGSR handle VBAT higher than VDD during normal operation?
The TPS3613-01DGSR isolates VBAT from VOUT when VBAT exceeds VDD - it does not connect the backup battery to the output rail unless VDD falls below the reset threshold (VIT ≈ 1.15 V) and VBAT is greater than VDD. This prevents reverse current flow and unintended discharge of the backup source. The internal 15-Ω switch only engages under those specific fault conditions, as detailed in the "Backup-Battery Switchover" section of the datasheet.
Can TPS3613-01DGSR be used with a 1.8 V microcontroller supply rail?
Yes - the TPS3613-01DGSR supports VDD from 1.65 V to 5.5 V and provides fully specified performance at 1.8 V, including 40 µA max supply current, 1.15 V sense threshold, and valid reset output drive (VOH ≥ VDD − 0.2 V, VOL ≤ 0.2 V). Its SENSE pin allows precise adjustment of the reset point for 1.8 V systems using external resistors, and the VSSOP package enables dense layout integration alongside modern low-voltage MCUs.
What is the purpose of the CEIN and CEOUT pins on TPS3613-01DGSR?
The CEIN and CEOUT pins implement chip-enable signal gating: CEIN accepts the processor's CE signal, and CEOUT delivers a conditioned version to external CMOS RAM. During normal operation, CEIN passes through to CEOUT with ≤3 ns delay; when reset is asserted, the path disables within 15 µs, forcing CEOUT high (to VOUT) and preventing memory writes during unstable power. This protects RAM contents during brownout - a core function explicitly documented in the "Chip-Enable Signal Gating" section.
Does TPS3613-01DGSR require external components to operate?
Yes - the TPS3613-01DGSR requires at minimum a 0.1 µF ceramic bypass capacitor between VDD and GND (per datasheet Figure 1 and Absolute Maximum Ratings note), plus external resistors on the SENSE pin to set the desired reset threshold voltage. For CE gating, no additional components are needed, but proper PCB layout (short traces, ground plane) is essential to maintain 3 ns propagation delay integrity. Optional pull-up/pull-down resistors may be used on MR or CEIN depending on system logic levels.
TPS3613-01DGSR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Battery Backup Circuit
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- Adjustable/Selectable
- Output:
- Push-Pull, Totem Pole
- Reset:
- Active High/Active Low
- Reset Timeout:
- 60ms Minimum
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-VSSOP
TPS3613-01DGSR FAQ
1.How can I place an order for TPS3613-01DGSR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS3613-01DGSR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS3613-01DGSR reliable?
The price and inventory of TPS3613-01DGSR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS3613-01DGSR is usually 5 days.
3.What payment methods are accepted for TPS3613-01DGSR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS3613-01DGSR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS3613-01DGSR?
TPS3613-01DGSR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS3613-01DGSR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS3613-01DGSR?
For technical support, including TPS3613-01DGSR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS3613-01DGSR requirements.
6.How does Aetrix verify that TPS3613-01DGSR is sourced from the original manufacturer or authorized distributors?
All TPS3613-01DGSR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS3613-01DGSR meets industry standards.
7.What is the process for return or replacement of TPS3613-01DGSR?
All TPS3613-01DGSR units undergo pre-shipment inspection (PSI). If there is an issue with TPS3613-01DGSR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS3613-01DGSR part is unused and in its original packaging.
Return procedure for TPS3613-01DGSR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TPS3613-01DGSR Tags
-
MIC826SYMT-TR
Microchip Technology
-
APX803S-31SA-7
Diodes Incorporated
-
APX803L20-29SA-7
Diodes Incorporated
-
TPS3828-33DBVR
Texas Instruments
-
V6340RSP3B+
EM Microelectronic
-
EM6325CXSP5B-2.9+
EM Microelectronic
-
MCP120T-300I/TT
Microchip Technology
-
MCP130T-315I/TT
Microchip Technology
-
MCP120T-475I/TT
Microchip Technology
-
MCP111T-300E/TT
Microchip Technology
-
MCP120T-315I/TT
Microchip Technology
-
MCP809T-315I/TT
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
