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Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Supervisors

Texas Instruments TPS3808G125QDBVRQ1

Name: TPS3808G125QDBVRQ1
Brand: Texas Instruments
SKU: TPS3808G125QDBVRQ1
Price: 2.40 USD
Availability: InStock
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Part No.:: TPS3808G125QDBVRQ1

Manufacturer:: Texas Instruments

Category:: Supervisors

Package:: SOT-23-6

Datasheet:: TPS3808G125QDBVRQ1.pdf

Description:: IC SUPERVISOR 1 CHANNEL SOT23-6

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Product details

Overview

TPS3808G125QDBVRQ1 from Texas Instruments is an automotive-grade, low-quiescent-current supervisory circuit in SOT-23-6 package, monitoring 1.25 V system rails with ±0.5% threshold accuracy, 2.4 μA typical supply current, and user-programmable reset delay from 1.25 ms to 10 s. It asserts an open-drain RESET signal during undervoltage or manual reset events in DSP, FPGA, and automotive radar power-up sequencing.

For engineers reviewing the TPS3808G125QDBVRQ1 datasheet, TPS3808G125QDBVRQ1 pinout, TPS3808G125QDBVRQ1 application, or TPS3808G125QDBVRQ1 equivalent, key selection criteria include its AEC-Q100 qualification, –40°C to +125°C operation, fixed 1.16 V sense threshold, CT-pin programmable timing, and SOT-23 footprint compatibility with space-constrained automotive control modules.

Technical Context

The TPS3808G125QDBVRQ1 implements a precision voltage comparator with built-in 0.5% threshold accuracy for V_IT ≤ 3.3 V and 1.5–2.5% hysteresis, coupled to a digitally controlled timer driven by a 220 nA internal current source charging the external CT capacitor. Its SENSE input accepts voltages from 0.4 V to 5 V, while VDD operates from 1.8 V to 6.5 V.

Reset assertion is triggered by either SENSE falling below 1.16 V (nominal) or MR pulled low, with RESET remaining active for the configured delay after both conditions clear. The open-drain output requires an external pullup resistor (10 kΩ–1 MΩ), enabling level-shifting above VDD and compatibility with diverse logic families in safety-critical automotive subsystems.

Key Specifications

Parameter	Value and Actual Design Meaning
Threshold Voltage (V_IT)	1.16 V nominal; enables precise supervision of 1.25 V core rails with ±0.5% accuracy over temperature.
Quiescent Current (I_DD)	2.4 μA typical at 3.3 V; supports ultra-low-power battery-backed systems and always-on automotive modules.
Reset Delay Range	1.25 ms to 10 s via CT capacitor; allows flexible power-up timing alignment across multi-rail SoCs without firmware intervention.
Operating Temperature	–40°C to +125°C junction; fully qualified for engine control units, ADAS sensors, and under-hood electronics.
ESD Rating (HBM)	±2000 V per AEC-Q100-002; ensures robustness against handling and board-level electrostatic discharge in production environments.
Supply Voltage Range	1.8 V to 6.5 V on VDD; accommodates wide-input DC/DC outputs and legacy 5 V domains while maintaining supervision integrity.
Output Type	Open-drain RESET; permits wired-OR configuration, voltage-level translation up to 6.5 V, and direct interface to microcontroller reset inputs.

Pinout & Package

SOT-23-6 package (2.90 mm × 1.60 mm body size) with exposed pad not present; suitable for reflow assembly and high-density PCB layouts in automotive ECUs.

Pin/Terminal	Circuit Role	Design Meaning
1: RESET	Open-drain output	Asserts low during undervoltage or MR event; requires external pullup; supports voltage levels beyond VDD.
2: GND	Ground reference	Primary return path for internal circuitry and RESET sink current; must connect to low-impedance system ground plane.
3: MR	Manual reset input	Active-low trigger; internally pulled up to VDD via 90 kΩ; initiates reset independent of SENSE voltage.
4: CT	Reset delay programming	Connects to external capacitor (≥100 pF) to set delay from 1.25 ms–10 s; floating = 20 ms, tied to VDD via 40–200 kΩ = 300 ms.
5: SENSE	Voltage monitoring input	Monitors 1.25 V rail directly; comparator triggers RESET when voltage drops below 1.16 V with 1–2.5% hysteresis.
6: VDD	Power supply input	Accepts 1.8–6.5 V; requires local 0.1 μF ceramic decoupling; powers internal reference and logic.

Key Features

Feature	Design Value
AEC-Q100 Grade 1 qualification	Validated for automotive applications with guaranteed operation from –40°C to +125°C junction temperature.
Precision 0.5% threshold accuracy	Ensures reliable reset assertion at exactly 1.16 V for 1.25 V rails, minimizing false resets and improving system stability.
220 nA CT current source	Enables predictable, temperature-stable reset delay timing using low-cost ceramic capacitors without trimming.
SENSE transient immunity	Rejects short negative spikes (<20 μs duration) on monitored rail, preventing spurious resets in electrically noisy vehicle environments.
Internal MR pullup resistor	90 kΩ internal VDD tie eliminates need for external pullup when MR is unused, reducing BOM count and layout area.

Applications

Automotive Radar Power Sequencing	DSP Core Voltage Monitoring
Use Scenario: Ensures clean power-up of 77 GHz radar transceivers by validating 1.25 V analog supply before enabling RF front-end and digital baseband. IC Role / Device Role / Timing Role: Supervises 1.25 V VCORE rail and generates programmable delay to coordinate ASIC initialization with PLL lock and ADC calibration. Use Value: Prevents metastability and latch-up in high-speed mixed-signal radar ICs by enforcing strict voltage and timing margins during cold start.	Use Scenario: Monitors 1.25 V I/O or core supply of automotive DSPs (e.g., TI C6000 series) during ignition cycle and sleep/wake transitions. IC Role / Device Role / Timing Role: Provides fail-safe reset assertion if VCORE dips below 1.16 V due to load transients or regulator dropout, with 20 ms fixed delay for stable brownout recovery. Use Value: Eliminates DSP lockup or corrupted FFT processing caused by undervoltage-induced instruction corruption in real-time control loops.
FPGA Configuration Integrity	ADAS Camera Module Reset Control
Use Scenario: Validates 1.25 V auxiliary rail powering FPGA configuration memory and I/O banks in surround-view ECU designs. IC Role / Device Role / Timing Role: Asserts open-drain RESET to FPGA's PROG_B pin only after 1.25 V rail stabilizes and remains valid for ≥1.25 ms, ensuring bitstream loading integrity. Use Value: Guarantees deterministic FPGA configuration by preventing premature deassertion of PROG_B during supply ramp, avoiding partial bitstream loads.	Use Scenario: Supervises 1.25 V image sensor interface supply in rear-view and driver-monitoring cameras operating in cabin temperature extremes. IC Role / Device Role / Timing Role: Generates 300 ms reset pulse (CT tied to VDD) to hold camera SoC in reset until all 1.25 V, 1.8 V, and 3.3 V rails settle within tolerance. Use Value: Avoids image artifacts and sensor initialization failures by enforcing synchronized power-good sequencing across multiple voltage domains.

Automotive Radar Power Sequencing

DSP Core Voltage Monitoring

Use Scenario: Ensures clean power-up of 77 GHz radar transceivers by validating 1.25 V analog supply before enabling RF front-end and digital baseband.

IC Role / Device Role / Timing Role: Supervises 1.25 V VCORE rail and generates programmable delay to coordinate ASIC initialization with PLL lock and ADC calibration.

Use Value: Prevents metastability and latch-up in high-speed mixed-signal radar ICs by enforcing strict voltage and timing margins during cold start.

Use Scenario: Monitors 1.25 V I/O or core supply of automotive DSPs (e.g., TI C6000 series) during ignition cycle and sleep/wake transitions.

IC Role / Device Role / Timing Role: Provides fail-safe reset assertion if VCORE dips below 1.16 V due to load transients or regulator dropout, with 20 ms fixed delay for stable brownout recovery.

Use Value: Eliminates DSP lockup or corrupted FFT processing caused by undervoltage-induced instruction corruption in real-time control loops.

FPGA Configuration Integrity

ADAS Camera Module Reset Control

Use Scenario: Validates 1.25 V auxiliary rail powering FPGA configuration memory and I/O banks in surround-view ECU designs.

IC Role / Device Role / Timing Role: Asserts open-drain RESET to FPGA's PROG_B pin only after 1.25 V rail stabilizes and remains valid for ≥1.25 ms, ensuring bitstream loading integrity.

Use Value: Guarantees deterministic FPGA configuration by preventing premature deassertion of PROG_B during supply ramp, avoiding partial bitstream loads.

Use Scenario: Supervises 1.25 V image sensor interface supply in rear-view and driver-monitoring cameras operating in cabin temperature extremes.

IC Role / Device Role / Timing Role: Generates 300 ms reset pulse (CT tied to VDD) to hold camera SoC in reset until all 1.25 V, 1.8 V, and 3.3 V rails settle within tolerance.

Use Value: Avoids image artifacts and sensor initialization failures by enforcing synchronized power-good sequencing across multiple voltage domains.

Equivalent & Alternatives

The following parts are listed as comparable options for similar supervisory circuit applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
TPS3808G12QDBVRQ1	Fixed 1.12 V threshold (for 1.2 V rails); identical package, timing, and quiescent current.	Designed for 1.2 V systems; not suitable for 1.25 V rails requiring tighter margin control.	Select when supervising legacy 1.2 V cores where 1.12 V threshold provides optimal noise margin.
TPS3808G15QDBVRQ1	Fixed 1.4 V threshold (for 1.5 V rails); same SOT-23-6 footprint and AEC-Q100 qualification.	Targets 1.5 V domains like certain DDR I/O supplies; lacks precision for 1.25 V rail supervision.	Choose for 1.5 V FPGA I/O banks or processor auxiliary rails where 1.4 V trip point aligns with design margin requirements.

Compared with TPS3808G12QDBVRQ1 and TPS3808G15QDBVRQ1, the TPS3808G125QDBVRQ1 delivers the exact 1.16 V threshold needed for robust 1.25 V rail supervision-reducing risk of premature reset assertion or failure to detect marginal undervoltage conditions in next-generation automotive processors.

Availability

TPS3808G125QDBVRQ1 is available at Aetrix Electronics and suitable for automotive radar, ADAS camera modules, and DSP-based engine control units requiring stable component supply with full AEC-Q100 traceability and long-term lifecycle support.

Supply support for TPS3808G125QDBVRQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader delivering analog, embedded processing, and connectivity solutions for automotive, industrial, and consumer markets.

The TPS3808Gxx-Q1 product line was engineered specifically for automotive power-supply supervision-delivering ultra-low quiescent current, high-accuracy thresholds, and extended temperature operation to meet stringent ISO 26262 functional safety readiness requirements.

FAQ

What is the exact threshold voltage of the TPS3808G125QDBVRQ1 and how is it specified?

The TPS3808G125QDBVRQ1 has a nominal threshold voltage (V_IT) of 1.16 V, corresponding to its 1.25 V rail supervision function. This value is factory-trimmed with ±0.5% accuracy over –40°C to +125°C, as confirmed in the Device Comparison Table and Electrical Characteristics section of the SBVS085J datasheet. The 1.16 V trip point ensures reliable detection of 1.25 V rail collapse while maintaining adequate noise margin.

How does the CT pin configure reset delay time on the TPS3808G125QDBVRQ1?

The CT pin on the TPS3808G125QDBVRQ1 controls reset delay via three configurations: floating yields 20 ms nominal delay; connection to VDD through a 40–200 kΩ resistor gives 300 ms; and connection to GND via a ≥100 pF capacitor enables user-programmable delays from 1.25 ms to 10 s. The internal 220 nA current source charges the capacitor to 1.23 V to terminate the delay, as detailed in Section 8.3.4 and Figure 13 of the datasheet.

Is the TPS3808G125QDBVRQ1 compatible with 3.3 V logic systems despite its 1.25 V threshold?

Yes-the TPS3808G125QDBVRQ1 is fully compatible with 3.3 V logic systems. Its VDD pin accepts 1.8–6.5 V, and its open-drain RESET output can be pulled up to 3.3 V (or higher) independently of VDD. The 1.25 V threshold applies only to the SENSE input; MR and RESET interface directly with 3.3 V microcontrollers and FPGAs without level shifters, as verified in the Recommended Operating Conditions table.

What automotive qualification does the TPS3808G125QDBVRQ1 meet?

The TPS3808G125QDBVRQ1 is qualified to AEC-Q100 Grade 1 standards, with full testing across –40°C to +125°C junction temperature. It meets HBM ESD rating of ±2000 V (per AEC-Q100-002) and CDM rating of ±1000 V (per AEC-Q100-011), as documented in Section 7.2 of the SBVS085J datasheet. This qualification covers automotive radar, ADAS, and powertrain control applications.

Can the TPS3808G125QDBVRQ1 monitor voltages other than 1.25 V?

No-the TPS3808G125QDBVRQ1 is a fixed-threshold device with a factory-set 1.16 V sense point optimized for 1.25 V rails. It cannot monitor arbitrary voltages; for adjustable thresholds down to 0.4 V, TI offers the TPS3808G01QDBVRQ1 variant. The "125" suffix explicitly denotes the 1.25 V rail version, as confirmed in the Device Comparison Table and orderable part number naming convention.

TPS3808G125QDBVRQ1 Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: -

Package/Case:: SOT-23-6

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Type:: Simple Reset/Power-On Reset

Number of Voltages Monitored:: 1

Voltage - Threshold:: 1.16V

Output:: Open Drain or Open Collector

Reset:: Active Low

Reset Timeout:: Adjustable/Selectable

Operating Temperature:: -40°C ~ 125°C (TJ)

Grade:: Automotive

Qualification:: AEC-Q100

Mounting Type:: Surface Mount

Supplier Device Package:: SOT-23-6

TPS3808G125QDBVRQ1 FAQ

1.How can I place an order for TPS3808G125QDBVRQ1 through Aetrix?

Please submit a Request for Quotation (RFQ) for TPS3808G125QDBVRQ1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

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The price and inventory of TPS3808G125QDBVRQ1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS3808G125QDBVRQ1 is usually 5 days.

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Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for TPS3808G125QDBVRQ1?

For technical support, including TPS3808G125QDBVRQ1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS3808G125QDBVRQ1 requirements.

6.How does Aetrix verify that TPS3808G125QDBVRQ1 is sourced from the original manufacturer or authorized distributors?

All TPS3808G125QDBVRQ1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS3808G125QDBVRQ1 meets industry standards.

7.What is the process for return or replacement of TPS3808G125QDBVRQ1?

All TPS3808G125QDBVRQ1 units undergo pre-shipment inspection (PSI). If there is an issue with TPS3808G125QDBVRQ1, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The TPS3808G125QDBVRQ1 part is unused and in its original packaging.

Return procedure for TPS3808G125QDBVRQ1:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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