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Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Supervisors

Texas Instruments TPS3808G12QDBVRQ1

Name: TPS3808G12QDBVRQ1
Brand: Texas Instruments
SKU: TPS3808G12QDBVRQ1
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: TPS3808G12QDBVRQ1

Manufacturer:: Texas Instruments

Category:: Supervisors

Package:: SOT-23-6

Datasheet:: TPS3808G12QDBVRQ1.pdf

Description:: IC SUPERVISOR 1 CHANNEL SOT23-6

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Product details

Overview

TPS3808G12QDBVRQ1 from Texas Instruments is an automotive-grade programmable-delay supervisory circuit designed to monitor 1.2 V system rails and assert an open-drain RESET signal upon undervoltage or manual reset assertion. It features 0.5% threshold accuracy, 2.4 μA typical quiescent current, –40°C to +125°C operation, and user-adjustable delay from 1.25 ms to 10 s via external capacitor on CT pin. Used in DSP, FPGA, and automotive vision systems for reliable power-on reset sequencing.

For engineers reviewing the TPS3808G12QDBVRQ1 datasheet, TPS3808G12QDBVRQ1 pinout, TPS3808G12QDBVRQ1 application, or TPS3808G12QDBVRQ1 equivalent, key selection criteria include fixed 1.12 V threshold (±0.5%), SOT-23-6 package compatibility, open-drain RESET output with external pullup requirement, and CT-pin-based delay configuration options (20 ms / 300 ms / programmable).

Technical Context

The TPS3808G12QDBVRQ1 implements a precision voltage comparator with internal 0.405 V reference and resistor divider to achieve 1.12 V nominal threshold (V_IT). Its reset timing is controlled by an on-chip 220 nA current source charging the external CT capacitor to 1.23 V - enabling accurate delay setting across temperature.

It operates over 1.8 V to 6.5 V supply range and supports dual reset triggers: SENSE voltage drop below V_IT or logic-low MR input. The open-drain RESET output requires external pullup (10 kΩ–1 MΩ), and the device includes built-in hysteresis (1–2.5% of V_IT) and immunity to short SENSE transients per overdrive-duration curve.

Key Specifications

Parameter	Value and Actual Design Meaning
Threshold Voltage (V_IT)	1.12 V ±0.5% - ensures precise 1.2 V rail monitoring with minimal false resets under temperature variation.
Quiescent Current (I_DD)	2.4 μA typical - enables battery-backed or ultra-low-power automotive subsystems without compromising supervision integrity.
Reset Delay Range	1.25 ms to 10 s - configurable via CT pin capacitor; supports both fast recovery (e.g., FPGA config) and long hold-off (e.g., processor boot stabilization).
Operating Temperature	–40°C to +125°C - qualified per AEC-Q100 Grade 1, suitable for under-hood and ADAS ECU environments.
Output Type	Open-drain RESET - allows level-shifting, wired-OR reset buses, and compatibility with diverse host logic families.
Supply Voltage Range	1.8 V to 6.5 V - powers from common intermediate rails (e.g., 3.3 V, 5 V) while monitoring lower-voltage cores (1.2 V).
SENSE Input Bias Current	±25 nA - minimizes loading on monitored rail and enables high-impedance sensing without significant voltage drop.

Pinout & Package

SOT-23-6 package (2.90 mm × 1.60 mm body size), surface-mount, lead-free, RoHS-compliant. Thermal pad not present in DBV variant.

Pin/Terminal	Circuit Role	Design Meaning
1: RESET	Open-drain output	Asserts low during reset condition; requires external pullup (10 kΩ–1 MΩ); can interface above VDD voltage.
2: GND	Ground reference	Primary return path for internal circuitry and SENSE comparator; must connect to low-impedance system ground plane.
3: MR	Manual reset input	Active-low trigger; internally pulled up to VDD (90 kΩ); drives RESET low when ≤0.3×VDD.
4: CT	Delay timing control	Connects to external capacitor (≥100 pF) for programmable delay; floating = 20 ms, tied to VDD via 40–200 kΩ = 300 ms.
5: SENSE	Voltage monitoring input	High-impedance node (±25 nA bias) for direct connection to 1.2 V rail; asserts RESET if voltage falls below 1.12 V.
6: VDD	Power supply input	Accepts 1.8–6.5 V; requires local 0.1 μF ceramic decoupling capacitor placed adjacent to pin.

Key Features

Feature	Design Value
AEC-Q100 qualified	Grade 1 (–40°C to +125°C), HBM ±2000 V - certified for automotive safety-critical power management.
Precision threshold accuracy	±0.5% for V_IT ≤3.3 V - eliminates need for external calibration in 1.2 V core monitoring applications.
Ultra-low quiescent current	2.4 μA typical - extends battery life in always-on vehicle modules (e.g., telematics, camera ECU).
Transient-immune SENSE input	Rejects <20 μs negative spikes per overdrive-duration curve - prevents spurious resets from switching noise.
Flexible reset delay configuration	Three modes: fixed 20 ms, fixed 300 ms, or 1.25 ms–10 s programmable - simplifies design across diverse boot timing requirements.

Applications

Automotive Vision ECUs	FPGA Configuration Sequencing
Use Scenario: Monitoring 1.2 V core supply of image signal processor (ISP) in ADAS camera module during cold crank and load dump conditions. IC Role / Device Role / Timing Role: Supervisory circuit asserting open-drain RESET to ISP until 1.2 V rail stabilizes post-power-up and remains asserted during brownout events. Use Value: Prevents ISP firmware corruption by ensuring reset hold time exceeds worst-case power rail settling (≥100 ms), enabled by 300 ms fixed delay mode.	Use Scenario: Coordinating power-up sequence of multi-rail FPGA (1.2 V core, 2.5 V I/O, 3.3 V auxiliary) where core voltage must be stable before configuration begins. IC Role / Device Role / Timing Role: Dedicated 1.2 V rail supervisor triggering FPGA PROG_B after verified core rail stability, using CT-capacitor-programmed 50 ms delay. Use Value: Eliminates need for discrete RC timing networks; achieves ±0.5% delay accuracy across temperature vs. ±20% for passive solutions.
DSP-Based Radar Signal Processing	Automotive Infotainment SoC Power Management
Use Scenario: Ensuring clean reset of 1.2 V DSP core in 77 GHz radar ECU after ignition cycle, including restart after watchdog timeout. IC Role / Device Role / Timing Role: Dual-trigger supervisor responding to either SENSE undervoltage or MR assertion from DSP's watchdog timer output. Use Value: Enables fail-safe recovery: MR-driven reset guarantees deterministic restart even if supply remains nominal but software hangs.	Use Scenario: Managing reset coordination between application processor (1.2 V), GPU (1.1 V), and DDR memory controller (1.2 V) in head-unit SoC platform. IC Role / Device Role / Timing Role: One TPS3808G12QDBVRQ1 per critical rail, with RESET outputs wire-OR'd to shared system reset bus. Use Value: Open-drain architecture allows safe aggregation of multiple supervisors onto single reset line without contention or voltage conflict.

Automotive Vision ECUs

FPGA Configuration Sequencing

Use Scenario: Monitoring 1.2 V core supply of image signal processor (ISP) in ADAS camera module during cold crank and load dump conditions.

IC Role / Device Role / Timing Role: Supervisory circuit asserting open-drain RESET to ISP until 1.2 V rail stabilizes post-power-up and remains asserted during brownout events.

Use Value: Prevents ISP firmware corruption by ensuring reset hold time exceeds worst-case power rail settling (≥100 ms), enabled by 300 ms fixed delay mode.

Use Scenario: Coordinating power-up sequence of multi-rail FPGA (1.2 V core, 2.5 V I/O, 3.3 V auxiliary) where core voltage must be stable before configuration begins.

IC Role / Device Role / Timing Role: Dedicated 1.2 V rail supervisor triggering FPGA PROG_B after verified core rail stability, using CT-capacitor-programmed 50 ms delay.

Use Value: Eliminates need for discrete RC timing networks; achieves ±0.5% delay accuracy across temperature vs. ±20% for passive solutions.

DSP-Based Radar Signal Processing

Automotive Infotainment SoC Power Management

Use Scenario: Ensuring clean reset of 1.2 V DSP core in 77 GHz radar ECU after ignition cycle, including restart after watchdog timeout.

IC Role / Device Role / Timing Role: Dual-trigger supervisor responding to either SENSE undervoltage or MR assertion from DSP's watchdog timer output.

Use Value: Enables fail-safe recovery: MR-driven reset guarantees deterministic restart even if supply remains nominal but software hangs.

Use Scenario: Managing reset coordination between application processor (1.2 V), GPU (1.1 V), and DDR memory controller (1.2 V) in head-unit SoC platform.

IC Role / Device Role / Timing Role: One TPS3808G12QDBVRQ1 per critical rail, with RESET outputs wire-OR'd to shared system reset bus.

Use Value: Open-drain architecture allows safe aggregation of multiple supervisors onto single reset line without contention or voltage conflict.

Equivalent & Alternatives

The following parts are listed as comparable options for similar supervisory circuit applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
TPS3808G33QDBVRQ1	Fixed 3.07 V threshold (vs. 1.12 V); identical package, timing, and quiescent current.	Monitors 3.3 V rails (e.g., I/O, analog supplies) instead of 1.2 V cores; not interchangeable without circuit redesign.	Select when supervising higher-voltage domains; same footprint and layout but different threshold resistor network.
MAX6326UT12D3+T	Fixed 1.14 V threshold, 3 μA I_DD, SOT-23-5 package, no CT pin - only fixed 200 ms delay.	Lacks programmable delay and MR input; simpler integration but no manual reset or timing flexibility.	Choose for cost-sensitive, space-constrained designs where 200 ms fixed delay suffices and MR is unused.

Compared with TPS3808G12QDBVRQ1, TPS3808G33QDBVRQ1 serves complementary voltage domains within the same system, while MAX6326UT12D3+T trades programmability for reduced pin count and BOM simplicity - making it suitable only for static timing requirements.

Availability

TPS3808G12QDBVRQ1 is available at Aetrix Electronics and suitable for automotive vision, radar signal processing, and infotainment SoC applications requiring stable component supply, AEC-Q100 compliance, and long-term production continuity.

Supply support for TPS3808G12QDBVRQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company delivering analog and embedded processing solutions, with leadership in automotive ICs, power management, and precision analog.

The TPS3808Gxx-Q1 product line delivers low-quiescent-current, AEC-Q100-qualified supervisory circuits specifically engineered for automotive ADAS, infotainment, and body electronics where reliability, accuracy, and extended temperature operation are mandatory.

FAQ

What is the exact threshold voltage of the TPS3808G12QDBVRQ1 and how tightly is it specified?

The TPS3808G12QDBVRQ1 has a nominal threshold voltage (V_IT) of 1.12 V, with guaranteed accuracy of ±0.5% over –40°C to +125°C. This specification applies specifically to devices with V_IT ≤3.3 V per the datasheet's Electrical Characteristics table, and is achieved using an internal precision reference and laser-trimmed resistive divider. The TPS3808G12QDBVRQ1 maintains this tolerance without external calibration.

Can the TPS3808G12QDBVRQ1 be used to monitor voltages other than 1.2 V?

No - the TPS3808G12QDBVRQ1 is factory-trimmed for a fixed 1.12 V threshold and cannot be adjusted to monitor other rails. For adjustable thresholds, TI offers the TPS3808G01QDBVRQ1 (0.405 V base, programmable down to 0.4 V with external resistors). Using TPS3808G12QDBVRQ1 on non-1.2 V rails risks incorrect reset assertion or failure to trigger.

What are the valid configurations for the CT pin on the TPS3808G12QDBVRQ1?

The CT pin on the TPS3808G12QDBVRQ1 supports three validated configurations: (1) left open for 20 ms nominal delay, (2) connected to VDD via 40–200 kΩ resistor for 300 ms nominal delay, or (3) connected to GND via ≥100 pF capacitor for programmable delay from 1.25 ms to 10 s. Floating CT without termination or connecting CT directly to GND without capacitor violates datasheet specifications and disables delay functionality.

Does the TPS3808G12QDBVRQ1 require an external pullup resistor on the RESET pin?

Yes - the TPS3808G12QDBVRQ1 features an open-drain RESET output and requires an external pullup resistor between RESET and the target logic supply (e.g., 3.3 V or 5 V). The datasheet specifies 10 kΩ to 1 MΩ; 50 kΩ is commonly used. Without this resistor, RESET cannot attain a valid high state, preventing proper deassertion and causing system boot failure.

Is the TPS3808G12QDBVRQ1 compatible with the standard SOT-23-6 footprint used by other TI supervisors?

Yes - the TPS3808G12QDBVRQ1 uses the industry-standard DBV (SOT-23-6) package with 2.90 mm × 1.60 mm body size and 0.95 mm pitch, matching pinout and land pattern of TI's TPS3808G33QDBVRQ1 and TPS3808G18QDBVRQ1. This enables direct PCB reuse across voltage variants when only threshold differs, provided layout accommodates identical thermal and decoupling requirements.

TPS3808G12QDBVRQ1 Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: -

Package/Case:: SOT-23-6

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Type:: Simple Reset/Power-On Reset

Number of Voltages Monitored:: 1

Voltage - Threshold:: 1.12V

Output:: Open Drain or Open Collector

Reset:: Active Low

Reset Timeout:: Adjustable/Selectable

Operating Temperature:: -40°C ~ 125°C (TJ)

Grade:: Automotive

Qualification:: AEC-Q100

Mounting Type:: Surface Mount

Supplier Device Package:: SOT-23-6

TPS3808G12QDBVRQ1 FAQ

1.How can I place an order for TPS3808G12QDBVRQ1 through Aetrix?

Please submit a Request for Quotation (RFQ) for TPS3808G12QDBVRQ1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for TPS3808G12QDBVRQ1 reliable?

The price and inventory of TPS3808G12QDBVRQ1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS3808G12QDBVRQ1 is usually 5 days.

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TPS3808G12QDBVRQ1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your TPS3808G12QDBVRQ1 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for TPS3808G12QDBVRQ1?

For technical support, including TPS3808G12QDBVRQ1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS3808G12QDBVRQ1 requirements.

6.How does Aetrix verify that TPS3808G12QDBVRQ1 is sourced from the original manufacturer or authorized distributors?

All TPS3808G12QDBVRQ1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS3808G12QDBVRQ1 meets industry standards.

7.What is the process for return or replacement of TPS3808G12QDBVRQ1?

All TPS3808G12QDBVRQ1 units undergo pre-shipment inspection (PSI). If there is an issue with TPS3808G12QDBVRQ1, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The TPS3808G12QDBVRQ1 part is unused and in its original packaging.

Return procedure for TPS3808G12QDBVRQ1:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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