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Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Supervisors

Texas Instruments TPS3808G15QDBVRQ1

Name: TPS3808G15QDBVRQ1
Brand: Texas Instruments
SKU: TPS3808G15QDBVRQ1
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: TPS3808G15QDBVRQ1

Manufacturer:: Texas Instruments

Category:: Supervisors

Package:: SOT-23-6

Datasheet:: TPS3808G15QDBVRQ1.pdf

Description:: IC SUPERVISOR 1 CHANNEL SOT23-6

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Product details

Overview

TPS3808G15QDBVRQ1 from Texas Instruments is an automotive-grade, low-quiescent-current supervisory circuit that monitors 1.5 V system rails and asserts an open-drain RESET signal upon undervoltage or manual reset assertion. It features 0.5% threshold accuracy, 2.4 μA typical supply current, and user-programmable reset delay from 1.25 ms to 10 s via external capacitor on CT pin. Used in DSP and microcontroller power sequencing for automotive vision and radar modules.

For engineers reviewing the TPS3808G15QDBVRQ1 datasheet, TPS3808G15QDBVRQ1 pinout, TPS3808G15QDBVRQ1 application, or TPS3808G15QDBVRQ1 equivalent, key selection criteria include its AEC-Q100 qualification, ±0.5% VIT accuracy at 1.4 V nominal threshold, SOT-23-6 package compatibility, and support for 20 ms / 300 ms fixed delays or fully programmable timing.

Technical Context

The TPS3808G15QDBVRQ1 implements a precision voltage comparator with built-in hysteresis (1–2.5% of VIT) and a programmable timer driven by a 220 nA internal current source charging the CT pin capacitor. Its SENSE input accepts voltages from 0.4 V to 5 V, but for this variant, the factory-set threshold is 1.4 V (±0.5%) corresponding to a 1.5 V nominal rail.

It operates across –40°C to +125°C junction temperature, supports 1.8 V to 6.5 V VDD supply, and uses an internal 90 kΩ pull-up on MR. The open-drain RESET output requires an external 10 kΩ–1 MΩ pull-up and remains asserted for the full delay period after both SENSE > VIT and MR > 0.7×VDD are satisfied.

Key Specifications

Parameter	Value and Actual Design Meaning
Reset Threshold (V_IT)	1.4 V ±0.5% - factory-trimmed for 1.5 V rail monitoring with high accuracy over temperature
Quiescent Current (I_DD)	2.4 μA typical - enables battery-backed systems and ultra-low-power automotive modules
Reset Delay Range	1.25 ms to 10 s - set via CT pin capacitor; fixed options: 20 ms (CT open) or 300 ms (CT→VDD via 40–200 kΩ)
Operating Temperature	–40°C to +125°C - qualified per AEC-Q100 Grade 1 for under-hood automotive applications
Output Type	Open-drain RESET - allows level-shifting, wired-OR configurations, and pull-up to voltage > VDD
Supply Voltage (V_DD)	1.8 V to 6.5 V - supports wide-input monitoring while powering internal circuitry independently
SENSE Input Bias Current	±25 nA - minimizes loading on monitored rail and enables high-impedance sensing networks

Pinout & Package

SOT-23-6 package (2.90 mm × 1.60 mm), surface-mount, lead-free, RoHS-compliant. Thermal pad not present in DBV variant.

Pin/Terminal	Circuit Role	Design Meaning
1: RESET	Open-drain output	Asserts low during reset condition; requires external pull-up resistor (10 kΩ–1 MΩ); supports voltage > VDD
2: GND	Ground reference	Primary return path for internal circuitry and RESET sink current; must connect to system ground plane
3: MR	Manual reset input	Active-low logic input; internally pulled up to VDD via 90 kΩ; drives RESET low when ≤0.3×VDD
4: CT	Delay timing control	Connects to external capacitor (≥100 pF) to set delay; floating = 20 ms, tied to VDD = 300 ms
5: SENSE	Voltage monitor input	Compares applied voltage against 1.4 V threshold; bias current ±25 nA; immune to transients <20 μs
6: VDD	Power supply input	Supplies internal circuitry (1.8–6.5 V); requires local 0.1 μF ceramic decoupling capacitor

Key Features

Feature	Design Value
AEC-Q100 Grade 1 qualification	Validated for automotive use from –40°C to +125°C ambient, supporting safety-critical ADAS subsystems
0.5% V_IT accuracy (≤3.3 V)	Ensures precise reset assertion at 1.4 V threshold without calibration, critical for 1.5 V core rail stability
Programmable reset delay (1.25 ms–10 s)	Enables matching of processor power-up timing requirements across diverse SoC families and boot sequences
2.4 μA typical quiescent current	Extends battery life in always-on automotive modules such as camera ECU wake-up supervisors
Immunity to SENSE pin transients	Rejects noise spikes <20 μs duration below V_IT, eliminating false resets in electrically noisy vehicle environments

Applications

Automotive Vision Systems	DSP Power Sequencing
Use Scenario: Monitors 1.5 V image sensor core supply in surround-view camera ECUs during cold cranking and load dump events. IC Role / Device Role / Timing Role: Supervisory circuit asserting open-drain RESET to SoC until 1.5 V rail stabilizes above 1.4 V with 100 ms programmable delay. Use Value: Prevents corrupted image capture or firmware lockup by ensuring DSP only exits reset after stable core voltage is confirmed.	Use Scenario: Coordinates power-up sequence between 1.5 V DSP core and 3.3 V I/O rails in radar signal processors. IC Role / Device Role / Timing Role: Generates delayed, synchronized RESET pulse to DSP after both rails exceed thresholds, using CT capacitor for precise 250 ms hold-off. Use Value: Eliminates race conditions during multi-rail power-up, guaranteeing deterministic boot state and avoiding bus contention.
Automotive Radar Modules	FPGA Configuration Supervision
Use Scenario: Validates 1.5 V analog front-end supply in 77 GHz radar transceivers exposed to thermal cycling and EMI. IC Role / Device Role / Timing Role: Provides high-accuracy (±0.5%) undervoltage detection and 300 ms fixed delay via CT→VDD resistor to accommodate slow LDO settling. Use Value: Ensures RF front-end biasing is fully established before digital baseband initialization, preventing spectral leakage or calibration errors.	Use Scenario: Guards FPGA configuration memory integrity during 1.5 V core rail brownout in ADAS domain controllers. IC Role / Device Role / Timing Role: Asserts RESET to FPGA's PROG_B pin when SENSE drops below 1.4 V, with 50 ms delay to allow flash read completion before reconfiguration. Use Value: Avoids partial bitstream loading and configuration failure by enforcing minimum power-valid window before FPGA release.

Automotive Vision Systems

DSP Power Sequencing

Use Scenario: Monitors 1.5 V image sensor core supply in surround-view camera ECUs during cold cranking and load dump events.

IC Role / Device Role / Timing Role: Supervisory circuit asserting open-drain RESET to SoC until 1.5 V rail stabilizes above 1.4 V with 100 ms programmable delay.

Use Value: Prevents corrupted image capture or firmware lockup by ensuring DSP only exits reset after stable core voltage is confirmed.

Use Scenario: Coordinates power-up sequence between 1.5 V DSP core and 3.3 V I/O rails in radar signal processors.

IC Role / Device Role / Timing Role: Generates delayed, synchronized RESET pulse to DSP after both rails exceed thresholds, using CT capacitor for precise 250 ms hold-off.

Use Value: Eliminates race conditions during multi-rail power-up, guaranteeing deterministic boot state and avoiding bus contention.

Automotive Radar Modules

FPGA Configuration Supervision

Use Scenario: Validates 1.5 V analog front-end supply in 77 GHz radar transceivers exposed to thermal cycling and EMI.

IC Role / Device Role / Timing Role: Provides high-accuracy (±0.5%) undervoltage detection and 300 ms fixed delay via CT→VDD resistor to accommodate slow LDO settling.

Use Value: Ensures RF front-end biasing is fully established before digital baseband initialization, preventing spectral leakage or calibration errors.

Use Scenario: Guards FPGA configuration memory integrity during 1.5 V core rail brownout in ADAS domain controllers.

IC Role / Device Role / Timing Role: Asserts RESET to FPGA's PROG_B pin when SENSE drops below 1.4 V, with 50 ms delay to allow flash read completion before reconfiguration.

Use Value: Avoids partial bitstream loading and configuration failure by enforcing minimum power-valid window before FPGA release.

Equivalent & Alternatives

The following parts are listed as comparable options for similar supervisory circuit applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
TPS3808G12QDBVRQ1	Fixed 1.12 V threshold (for 1.2 V rails); identical package, timing, and quiescent current	Used where system core voltage is 1.2 V instead of 1.5 V; same automotive qualification and pinout	Select when monitoring 1.2 V rails; no layout change required but threshold mismatch invalidates 1.5 V use
TPS3808G33QDBVRQ1	Fixed 3.07 V threshold (for 3.3 V rails); otherwise identical electrical specs and SOT-23-6 footprint	Applied to I/O or auxiliary supply supervision rather than 1.5 V core; shares same delay programming and MR interface	Choose for 3.3 V rail monitoring; pin-compatible but threshold unsuitable for 1.5 V core validation

Compared with TPS3808G15QDBVRQ1, the TPS3808G12QDBVRQ1 and TPS3808G33QDBVRQ1 offer identical timing, packaging, and automotive qualification-but differ exclusively in factory-trimmed reset thresholds, requiring explicit rail-voltage alignment to avoid undervoltage detection errors.

Availability

TPS3808G15QDBVRQ1 is available at Aetrix Electronics and suitable for automotive vision systems, radar modules, DSP power sequencing, and FPGA configuration supervision requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for TPS3808G15QDBVRQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company delivering analog and embedded processing solutions, with leadership in automotive ICs and high-reliability power management.

The TPS3808Gxx-Q1 product line delivers AEC-Q100-qualified supervisory circuits optimized for automotive microprocessor, DSP, and FPGA power integrity-designed to ensure deterministic reset behavior under harsh electrical and thermal conditions.

FAQ

What is the exact reset threshold voltage of the TPS3808G15QDBVRQ1?

The TPS3808G15QDBVRQ1 has a factory-trimmed negative-going input threshold (V_IT) of 1.4 V ±0.5% over –40°C to +125°C. This corresponds to nominal supervision of a 1.5 V rail and is specified in the Electrical Characteristics table of the SBVS085J datasheet under "V_IT Negative-going input threshold accuracy" for TPS3808G15-Q1 variants.

How is the reset delay time configured on the TPS3808G15QDBVRQ1?

The TPS3808G15QDBVRQ1 reset delay is set via the CT pin: leave CT open for 20 ms nominal delay, tie CT to VDD through a 40–200 kΩ resistor for 300 ms nominal delay, or connect CT to GND via a ≥100 pF capacitor for user-programmable delay from 1.25 ms to 10 s. Equation 1 in the datasheet calculates C_T = (t_D − 0.5 ms) / 175, where t_D is in seconds.

Does the TPS3808G15QDBVRQ1 support operation below 1.8 V supply?

No-the TPS3808G15QDBVRQ1 requires a minimum V_DD of 1.8 V per Recommended Operating Conditions (Section 7.3). Although it monitors down to 0.4 V on the SENSE pin, the internal circuitry-including reference, comparator, and timer-requires ≥1.8 V on VDD to function correctly and maintain 0.5% threshold accuracy.

Is the TPS3808G15QDBVRQ1 pin-compatible with other TPS3808Gxx-Q1 variants in SOT-23-6?

Yes-TPS3808G15QDBVRQ1 uses the DBV (SOT-23-6) package and shares identical pin configuration and function mapping with all TPS3808Gxx-Q1 variants in the same package, including TPS3808G12QDBVRQ1 and TPS3808G33QDBVRQ1. Pin 1 is RESET, Pin 2 is GND, Pin 3 is MR, Pin 4 is CT, Pin 5 is SENSE, and Pin 6 is VDD.

What is the maximum capacitive load the RESET output can drive on the TPS3808G15QDBVRQ1?

The TPS3808G15QDBVRQ1 RESET pin is an open-drain output rated for 5 mA sink current (Absolute Maximum Ratings, Section 7.1). While the datasheet specifies test conditions with C_L = 50 pF, the output can reliably drive larger capacitive loads-such as FPGA PROG_B inputs-provided the external pull-up resistor value is reduced to maintain rise time and voltage margin, per application note SLVA612.

TPS3808G15QDBVRQ1 Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: -

Package/Case:: SOT-23-6

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Type:: Simple Reset/Power-On Reset

Number of Voltages Monitored:: 1

Voltage - Threshold:: 1.4V

Output:: Open Drain or Open Collector

Reset:: Active Low

Reset Timeout:: 180ms Minimum

Operating Temperature:: -40°C ~ 125°C (TJ)

Grade:: Automotive

Qualification:: AEC-Q100

Mounting Type:: Surface Mount

Supplier Device Package:: SOT-23-6

TPS3808G15QDBVRQ1 FAQ

1.How can I place an order for TPS3808G15QDBVRQ1 through Aetrix?

Please submit a Request for Quotation (RFQ) for TPS3808G15QDBVRQ1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for TPS3808G15QDBVRQ1 reliable?

The price and inventory of TPS3808G15QDBVRQ1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS3808G15QDBVRQ1 is usually 5 days.

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Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for TPS3808G15QDBVRQ1?

For technical support, including TPS3808G15QDBVRQ1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS3808G15QDBVRQ1 requirements.

6.How does Aetrix verify that TPS3808G15QDBVRQ1 is sourced from the original manufacturer or authorized distributors?

All TPS3808G15QDBVRQ1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS3808G15QDBVRQ1 meets industry standards.

7.What is the process for return or replacement of TPS3808G15QDBVRQ1?

All TPS3808G15QDBVRQ1 units undergo pre-shipment inspection (PSI). If there is an issue with TPS3808G15QDBVRQ1, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The TPS3808G15QDBVRQ1 part is unused and in its original packaging.

Return procedure for TPS3808G15QDBVRQ1:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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