Texas Instruments TPS3808G25DBVT

Overview

TPS3808G25DBVT from Texas Instruments is a low-quiescent-current, programmable-delay supervisory circuit designed to monitor 2.5-V system rails and assert an open-drain RESET signal when the SENSE voltage drops below 2.33 V or MR is pulled low. It delivers 0.5% threshold accuracy, 2.4 μA typical supply current, and user-adjustable reset delay from 1.25 ms to 10 s-enabling reliable power-on reset in battery-powered microcontroller systems.

For engineers reviewing the TPS3808G25DBVT datasheet, TPS3808G25DBVT pinout, TPS3808G25DBVT application, or TPS3808G25DBVT equivalent, key selection considerations include its fixed 2.33-V threshold for 2.5-V rails, SOT-23-6 package compatibility, open-drain RESET output with external pull-up requirement, and operation across –40°C to 125°C for industrial embedded designs.

Technical Context

The TPS3808G25DBVT implements a precision voltage comparator with built-in hysteresis (1% of VIT) and an on-chip 220-nA current source that charges an external CT capacitor to set reset delay. Its SENSE input monitors system voltage directly, while MR provides asynchronous manual reset with 90-kΩ internal pull-up.

RESET assertion is triggered by either SENSE falling below 2.33 V or MR dropping below 0.3×VDD; de-assertion requires both inputs to return above their thresholds plus the full programmed delay. The device operates from 1.7 V to 6.5 V and maintains stable performance across temperature via a precision reference achieving ±0.5% VIT accuracy for VIT ≤ 3.3 V.

Key Specifications

Pinout & Package

SOT-23-6 (DBV) package: 2.90 mm × 1.60 mm body, 0.95 mm height, gull-wing leads, RoHS-compliant matte tin lead finish, MSL Level-1.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar supervisory circuit applications.

Compared with TPS3808G25DBVT, the DBVR offers identical performance in bulk packaging for production, while the MAX6326UT25+T sacrifices flexibility (no MR, fixed delay) and efficiency (1.5× higher IQ) for cost-sensitive, minimal-feature applications.

Availability

TPS3808G25DBVT is available at Aetrix Electronics and suitable for microcontroller power-on reset, battery-powered edge sensor nodes, FPGA configuration integrity, and industrial motor control board applications requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for TPS3808G25DBVT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company delivering analog and embedded processing solutions for industrial, automotive, and personal electronics markets.

The TPS3808 family is engineered for high-accuracy, ultra-low-power system supervision-specifically targeting applications where precise voltage monitoring, programmable reset timing, and extended temperature operation are critical.

FAQ

What is the exact threshold voltage of the TPS3808G25DBVT and how is it calibrated?

The TPS3808G25DBVT has a nominal threshold voltage of 2.33 V, corresponding to 2.5-V rail supervision. This value is factory-trimmed using a precision internal reference, achieving ±0.5% accuracy over –40°C to 125°C for VIT ≤ 3.3 V. No external calibration is required-the tolerance is guaranteed per TI's production test flow and documented in Section 7.5 of the SBVS050M datasheet. The TPS3808G25DBVT maintains this accuracy without drift across its full operating temperature and supply range.

Can the TPS3808G25DBVT be used to monitor voltages other than 2.5 V?

No-the TPS3808G25DBVT is a fixed-threshold variant optimized exclusively for 2.5-V rails with a 2.33-V trip point. To monitor other voltages, select a different member of the TPS3808 family (e.g., TPS3808G33 for 3.3 V or TPS3808G01 for adjustable thresholds). The TPS3808G25DBVT does not support external resistor dividers on the SENSE pin; its internal reference is hardwired to 2.33 V, and using it outside its specified rail violates the recommended operating conditions in Section 7.3.

What is the minimum and maximum reset delay time achievable with the TPS3808G25DBVT?

The TPS3808G25DBVT supports a reset delay range of 1.25 ms to 10 s, set by the CT pin configuration. With CT open, delay is fixed at 20 ms; with CT tied to VDD via 40–200 kΩ, it is 300 ms; with CT connected to a ground-referenced capacitor ≥100 pF, delay follows t_D(s) = C_T(nF) × 10⁻⁹ + 0.5 × 10⁻³. For example, 180 nF yields ~1.2 s. All delays are specified over –40°C to 125°C and depend on capacitor tolerance and leakage-low-leakage ceramic capacitors are mandatory for accuracy. The TPS3808G25DBVT does not support delays shorter than 1.25 ms or longer than 10 s.

Does the TPS3808G25DBVT require an external pull-up resistor on the RESET pin?

Yes-the TPS3808G25DBVT features an open-drain RESET output and requires an external pull-up resistor between RESET and the target logic supply (e.g., 3.3 V or 5 V). TI specifies 10 kΩ to 1 MΩ; 100 kΩ is commonly used. This resistor defines the logic-high voltage and ensures proper rise time. Without it, RESET remains floating and cannot drive a valid high state. The TPS3808G25DBVT's open-drain architecture also allows level-shifting-e.g., pulling RESET to 5 V while VDD is 2.5 V-as long as the pull-up voltage stays within absolute maximum ratings (≤6.5 V).

How does the manual reset (MR) pin function on the TPS3808G25DBVT?

The MR pin on the TPS3808G25DBVT is an active-low, CMOS-compatible input with an internal 90-kΩ pull-up to VDD. Driving MR below 0.3×VDD asserts RESET immediately, independent of SENSE voltage. When MR returns high and SENSE exceeds 2.33 V, RESET remains low for the full programmed delay before de-asserting. If unused, MR may be left floating-the internal pull-up ensures it defaults to logic high. The TPS3808G25DBVT's MR pin enables system-level reset coordination, such as initiating reboot from a watchdog timer or host processor, and is electrically validated across –40°C to 125°C.