Texas Instruments TPS3870J4330DSERQ1
- Part No.:
- TPS3870J4330DSERQ1
- Manufacturer:
- Texas Instruments
- Category:
- Supervisors
- Package:
- 6-WFDFN
- Datasheet:
-
TPS3870J4330DSERQ1.pdf
- Description:
- IC SUPERVISOR 1 CHANNEL 6WSON
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TPS3870J4330DSERQ1 from Texas Instruments is an AEC-Q100 Grade 1 automotive overvoltage reset IC in a 6-pin WSON (DSE) package, monitoring supply rails with ±0.7% threshold accuracy across –40°C to +125°C, fixed 3.30 V OV trip point, 4% tolerance, and dual-mode time delay (10 ms or 200 ms) selectable via CT pin configuration. It serves as a safety-critical voltage supervisor for processor core rail monitoring in ADAS and HEV/EV power domains.
For engineers reviewing the TPS3870J4330DSERQ1 datasheet, TPS3870J4330DSERQ1 pinout, TPS3870J4330DSERQ1 application, or TPS3870J4330DSERQ1 equivalent, key selection considerations include its ±0.7% OV threshold accuracy over temperature, open-drain active-low RESET output with latch mode, manual reset (MR) support, internal glitch immunity (3.5 µs at 5% overdrive), and programmable time delay using a single external capacitor on CT.
Technical Context
The TPS3870J4330DSERQ1 implements a precision comparator with trimmed internal resistor divider and reference, eliminating external components for threshold setting. Its OV detection path includes built-in hysteresis (0.3–0.8% of VIT+) and analog glitch filtering to prevent false resets during transients.
Time delay is determined by CT pin state: floating → 10 ms nominal, pulled to VDD via 10 kΩ → 200 ms nominal, or connected to ground via capacitor → user-programmable delay (e.g., 0.1–1000 nF yields ~0.1–500 ms). MR input supports logic-level hard reset with 1 µs minimum pulse width and 500 ns propagation delay.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| OV Threshold | Fixed 3.30 V with ±0.7% accuracy over –40°C to +125°C - enables tight-margin core rail supervision without calibration. |
| Supply Range | 1.7 V to 5.5 V - supports direct connection to low-voltage MCU I/O rails or intermediate power domains. |
| Quiescent Current | 7 µA max - ensures minimal impact on battery-backed or always-on automotive subsystems. |
| Reset Output | Open-drain active-low with 250 mV VOL at 5 mA - compatible with 1.8 V/3.3 V/5 V logic interfaces using external pull-up. |
| Time Delay Options | 10 ms (CT open) or 200 ms (CT = VDD via 10 kΩ) - factory-trimmed delays eliminate timing component variability. |
| Hysteresis | 0.3–0.8% of VIT+ - prevents oscillation near threshold during slow-ramp or noisy supply conditions. |
| Glitch Immunity | 3.5 µs at 5% overdrive on SENSE - rejects short-duration transients without requiring external RC filtering. |
Pinout & Package
Package: 6-pin WSON (DSE), 1.50 mm × 1.50 mm, 0.5 mm pitch, wettable flank - optimized for automotive PCB assembly and thermal performance (RθJA = 184.2°C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 SENSE | Monitored voltage input | High-impedance comparator input; connects directly to VCORE or DC/DC output; no external resistors needed. |
| 2 VDD | Supply input | Power source for internal circuitry; UVLO activates below 1.7 V; requires local 0.1 µF ceramic bypass. |
| 3 CT | Capacitor time delay control | Selects reset delay mode: floating = 10 ms, VDD-biased = 200 ms, capacitor-to-GND = programmable delay. |
| 4 RESET | Active-low open-drain output | Latches low during OV or MR assertion; requires external pull-up; drives processor reset or LDO enable. |
| 5 GND | Ground reference | Analog and digital common return; must be low-impedance connection to system ground plane. |
| 6 MR | Manual reset input | Pull low ≤0.3 V to force RESET assertion; internally pulled up to VDD; 1 µs min pulse width required. |
Key Features
| Feature | Design Value |
|---|---|
| AEC-Q100 Grade 1 qualification | Validated for –40°C to +125°C ambient operation - meets functional safety requirements for ADAS and powertrain systems. |
| Internal precision voltage reference | ±0.25% typical accuracy at 25°C - eliminates external resistor matching errors and reduces BOM count. |
| Dual-mode time delay architecture | Factory-trimmed fixed delays (10/200 ms) + capacitor-programmable option - provides flexibility without compromising timing precision. |
| Redundant sensing path | Separate SENSE and VDD pins - enables independent monitoring of core rail while powering supervisor from auxiliary supply. |
| Integrated glitch immunity | 3.5 µs rejection window on SENSE - removes need for external RC filters in high-noise automotive environments. |
Applications
| Advanced Driver Assistance Systems (ADAS) | Automotive Camera Modules |
|---|---|
|
Use Scenario: Monitoring 3.3 V core supply for radar SoC during cold cranking and load dump events. IC Role / Device Role / Timing Role: Overvoltage supervisor asserting latched RESET signal if VCORE exceeds 3.30 V ±0.7%, preventing SoC latch-up or data corruption. Use Value: ±0.7% threshold accuracy ensures reliable trip before 3.3 V rail exceeds MCU's absolute maximum rating (typically 3.6 V), even at 125°C junction temperature. |
Use Scenario: Supervising 3.3 V image sensor interface power in surround-view camera ECU. IC Role / Device Role / Timing Role: Detecting overvoltage on sensor I/O rail and holding processor in reset until condition clears, with 10 ms delay to avoid nuisance trips during transient coupling. Use Value: Open-drain RESET output interfaces directly to 3.3 V FPGA reset pin; MR pin allows host MCU to initiate controlled reinitialization after firmware update. |
| Hybrid Electric Vehicle (HEV) Battery Management | FPGA-Based Automotive Gateway |
|
Use Scenario: Protecting isolated communication ICs powered from 3.3 V DC/DC converter fed by 12 V battery bus. IC Role / Device Role / Timing Role: OV monitor on secondary side of isolated DC/DC; asserts RESET if primary-side transients propagate through isolation barrier. Use Value: 200 ms delay (CT = VDD) prevents false resets during brief 12 V bus spikes; internal hysteresis avoids chatter near 3.30 V threshold. |
Use Scenario: Ensuring clean startup of Xilinx Zynq-based gateway controller after 3.3 V domain powers up. IC Role / Device Role / Timing Role: Voltage supervisor generating synchronized reset pulse with 10 ms hold time, timed independently of main power sequencer. Use Value: Separate SENSE/VDD pins allow monitoring of FPGA core rail while drawing bias from auxiliary 5 V supply - critical for fault-isolated power architectures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar overvoltage reset applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS3870J4330DSER | Non-automotive grade (no AEC-Q100); same electrical specs and pinout. | Not qualified for automotive safety-critical systems; suitable for industrial or consumer designs. | Select when AEC-Q100 compliance is not required and cost optimization is prioritized. |
| TLV809E33DBZR | Fixed 3.3 V OV threshold but only ±1.5% accuracy over temperature; no programmable time delay; SOT-23-3 package. | Lacks CT pin flexibility and automotive qualification; limited to basic reset functions without latch or MR. | Choose for space-constrained non-automotive applications where ±1.5% accuracy suffices and delay programming is unnecessary. |
Compared with TPS3870J4330DSERQ1, the TPS3870J4330DSER offers identical functionality without AEC-Q100 validation, while TLV809E33DBZR trades accuracy, timing flexibility, and automotive qualification for smaller footprint and lower cost in non-safety applications.
Availability
TPS3870J4330DSERQ1 is available at Aetrix Electronics and suitable for advanced driver assistance systems (ADAS), automotive camera modules, and hybrid electric vehicle (HEV) battery management requiring stable component supply with full automotive qualification traceability.
Supply support for TPS3870J4330DSERQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog and embedded processing technologies, with leadership in automotive-grade power management and signal chain solutions.
The TPS3870-Q1 product line delivers high-accuracy overvoltage supervision for safety-critical automotive subsystems, designed specifically to meet AEC-Q100 Grade 1 requirements and simplify power-rail monitoring in ADAS, infotainment, and electrification platforms.
FAQ
What is the overvoltage threshold voltage and accuracy of the TPS3870J4330DSERQ1?
The TPS3870J4330DSERQ1 has a fixed overvoltage threshold of 3.30 V with ±0.7% accuracy over the full operating temperature range of –40°C to +125°C. This specification is guaranteed in production testing and applies to all units shipped. The TPS3870J4330DSERQ1 achieves this accuracy using an internal trimmed resistor divider and precision voltage reference, eliminating dependency on external component tolerances.
How does the CT pin configure the reset time delay for the TPS3870J4330DSERQ1?
The CT pin on the TPS3870J4330DSERQ1 selects among three time delay modes: floating → 10 ms nominal delay, pulled to VDD via 10 kΩ → 200 ms nominal delay, or connected to ground via capacitor → user-programmable delay (e.g., 100 nF yields ~20 ms). The device evaluates CT state each time SENSE enters the valid window, with a 450 µs detection latency. All modes are factory-trimmed for precision.
Does the TPS3870J4330DSERQ1 support manual reset functionality?
Yes, the TPS3870J4330DSERQ1 includes a dedicated MR (manual reset) input pin. Driving MR low ≤0.3 V for ≥1 µs forces the RESET output low regardless of SENSE voltage. After MR returns high, RESET remains low for the full reset delay time (tD) before deasserting, provided SENSE is within the safe window. When unused, MR may be left floating due to internal VDD pull-up.
What package type and thermal characteristics does the TPS3870J4330DSERQ1 use?
The TPS3870J4330DSERQ1 uses a 6-pin WSON (DSE) package measuring 1.50 mm × 1.50 mm with 0.5 mm pitch. Its thermal resistance is RθJA = 184.2°C/W (junction-to-ambient) and RθJB = 86.4°C/W (junction-to-board), supporting operation up to +125°C ambient. The wettable flank design enables automated optical inspection (AOI) in automotive PCB assembly.
Is the TPS3870J4330DSERQ1 pin-compatible with other members of the TPS3870-Q1 family?
Yes, all TPS3870-Q1 variants-including TPS3870J4330DSERQ1-share identical 6-pin WSON (DSE) packaging and pinout. Electrical differences (threshold voltage, time delay options, tolerance) are implemented internally and do not affect board layout. This allows drop-in replacement across voltage and timing variants during design iteration or supply chain substitution.
TPS3870J4330DSERQ1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 6-WFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Simple Reset/Power-On Reset
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- 3.3V
- Output:
- Open Drain or Open Collector
- Reset:
- Active Low
- Reset Timeout:
- 140ms Minimum
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-WSON (1.5x1.5)
TPS3870J4330DSERQ1 FAQ
1.How can I place an order for TPS3870J4330DSERQ1 through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS3870J4330DSERQ1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS3870J4330DSERQ1 reliable?
The price and inventory of TPS3870J4330DSERQ1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS3870J4330DSERQ1 is usually 5 days.
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TPS3870J4330DSERQ1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS3870J4330DSERQ1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS3870J4330DSERQ1?
For technical support, including TPS3870J4330DSERQ1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS3870J4330DSERQ1 requirements.
6.How does Aetrix verify that TPS3870J4330DSERQ1 is sourced from the original manufacturer or authorized distributors?
All TPS3870J4330DSERQ1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS3870J4330DSERQ1 meets industry standards.
7.What is the process for return or replacement of TPS3870J4330DSERQ1?
All TPS3870J4330DSERQ1 units undergo pre-shipment inspection (PSI). If there is an issue with TPS3870J4330DSERQ1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS3870J4330DSERQ1 part is unused and in its original packaging.
Return procedure for TPS3870J4330DSERQ1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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