Texas Instruments TPS389015DSER

Overview

TPS389015DSER from Texas Instruments is a precision voltage supervisor IC designed for system power-rail monitoring and reset generation in space-constrained, low-power applications. It features a fixed 1.5 V nominal threshold (VITN = 1.44 V, VITP = 1.449 V), ±1% threshold accuracy over –40°C to +125°C, user-programmable reset delay (40 μs to 30 s via CT pin), 2.1 μA typical quiescent current, and open-drain RESET output. It is used to ensure reliable power-on sequencing and brownout protection for microcontrollers and FPGAs.

For engineers reviewing the TPS389015DSER datasheet, TPS389015DSER pinout, TPS389015DSER application, or TPS389015DSER equivalent, key selection criteria include its 1.44 V negative threshold with 0.325–0.825% hysteresis, CT-capacitor-based delay configurability, MR input support, and operation across 1.5–5.5 V supply range - all critical for battery-powered and automotive-grade embedded systems requiring stable reset behavior under thermal stress.

Technical Context

The TPS389015DSER implements a precision bandgap reference and comparator architecture to achieve ±1% threshold accuracy across temperature. Its internal CT pin current source (1.15 µA typ) charges an external capacitor to set the rising-edge reset delay, while built-in hysteresis ensures noise immunity on the SENSE input.

It operates in three functional modes: undefined below VPOR (0.8 V), asserted during undervoltage lockout (VPOR < VDD < 1.5 V), and fully active above VDD(min) = 1.5 V. The open-drain RESET output supports rail-independent pull-up (up to 5.5 V), enabling interface compatibility with diverse logic families.

Key Specifications

Pinout & Package

TPS389015DSER is housed in a 1.5-mm × 1.5-mm, 6-pin WSON (DSE) package with wettable flanks, optimized for automated optical inspection and high-density PCB layouts.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar voltage supervisor applications.

Compared with TPS389015DSER, TPS389012DSER offers identical functionality at a different threshold but requires redesign for 1.5 V rails, while MAX6326UT29D3+T sacrifices configurability for lower BOM count and smaller footprint - making TPS389015DSER optimal for adaptive, thermally demanding, or battery-critical designs.

Availability

TPS389015DSER is available at Aetrix Electronics and suitable for microcontroller power sequencing, FPGA configuration monitoring, battery-powered edge nodes, and industrial PLC I/O modules requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for TPS389015DSER includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company delivering analog and embedded processing solutions, with leadership in power management, signal chain, and high-reliability IC design.

The TPS3890 family was developed to address demand for ultra-low-power, high-accuracy supervisors in portable, automotive, and industrial systems - specifically targeting applications where traditional 10–20 µA supervisors drain battery reserves or lack thermal stability.

FAQ

What is the exact threshold voltage of the TPS389015DSER and how does it vary with temperature?

The TPS389015DSER has a nominal negative threshold voltage (VITN) of 1.44 V and positive threshold (VITP) of 1.449 V. Over –40°C to +125°C, VITN accuracy is guaranteed within ±1%, with typical deviation shown in Figure 2 of the datasheet: ±0.25% at 25°C, widening to ±0.75% at extremes. This ensures robust 1.5 V rail supervision without recalibration.

Can the TPS389015DSER monitor a voltage rail higher than its VDD supply?

Yes. The SENSE pin of the TPS389015DSER accepts input voltages from 0 V to 5.5 V (7 V absolute maximum), independent of the VDD supply voltage (1.5–5.5 V). This allows direct monitoring of 3.3 V or 5 V rails even when VDD is powered from a lower 1.8 V or 2.5 V source - eliminating external level-shifters or resistor dividers.

How is the reset delay time calculated for the TPS389015DSER using the CT pin?

The rising-edge reset delay (tPD(r)) of the TPS389015DSER is calculated as tPD(r) = CCT × VCT ÷ ICT + tPD(r)(nom), where CCT is the CT capacitor value in farads, VCT = 1.23 V (typ), ICT = 1.15 µA (typ), and tPD(r)(nom) = 25 µs. For example, a 100 nF capacitor yields ~107 ms delay. Ceramic capacitors are recommended to minimize leakage-induced error.

Does the TPS389015DSER require an external pull-up resistor on the RESET pin?

Yes. The RESET pin is open-drain, so an external pull-up resistor (10 kΩ to 1 MΩ) is mandatory to define the logic-high state. The resistor must connect to the target logic rail (e.g., 1.8 V, 3.3 V, or 5 V), which may differ from VDD. Pull-up value affects rise time and power consumption - 100 kΩ is typical for balanced speed and current draw.

What is the minimum VDD voltage required for the TPS389015DSER to assert a valid RESET signal?

The TPS389015DSER requires VDD ≥ 1.5 V to operate in normal mode and assert a valid RESET signal. Below 1.5 V but above 0.8 V (VPOR), RESET is forced low regardless of SENSE or MR state. Below 0.8 V, RESET behavior is undefined and must not be relied upon - ensuring failsafe behavior during deep undervoltage conditions.