Texas Instruments TPS389025DSET

Overview

TPS389025DSET from Texas Instruments is a precision voltage supervisor IC designed for system power-rail monitoring and reset generation in space-constrained, low-power applications. It features a fixed 2.5 V nominal threshold (VITN = 2.40 V, VITP = 2.414 V), ±1% accuracy over –40°C to +125°C, 2.1 µA typical quiescent current, open-drain RESET output, and user-programmable delay (40 µs to 30 s) via external CT capacitor. It is used to ensure reliable power-on reset for microcontrollers operating from 2.5 V rails.

For engineers reviewing the TPS389025DSET datasheet, TPS389025DSET pinout, TPS389025DSET application, or TPS389025DSET equivalent, key selection criteria include threshold accuracy at temperature extremes, CT-based delay configurability, MR input support for system-initiated resets, and compatibility with 1.5-mm × 1.5-mm WSON packaging for high-density PCB layouts.

Technical Context

The TPS389025DSET implements a precision bandgap reference and comparator architecture to achieve 1% threshold accuracy across –40°C to +125°C, with hysteresis of 0.325–0.825% to prevent chatter during rail recovery. Its CT pin uses a 1.15 µA internal current source charging an external capacitor to set the rising-edge RESET delay, with timing governed by tPD(r) = CCT × 1.07 + 25 µs (nominal).

It operates from 1.5 V to 5.5 V supply (VDD), monitors SENSE voltages up to 5.5 V independent of VDD, supports manual reset assertion via MR input (VIL = 0.25×VDD), and drives RESET as an open-drain output capable of sinking up to 20 mA with VOL ≤ 0.25 V at IRESET = 0.4 mA (VDD ≥ 1.5 V).

Key Specifications

Pinout & Package

TPS389025DSET is housed in a 6-pin, 1.5-mm × 1.5-mm WSON (DSE) package with wettable flanks, optimized for automated optical inspection and thermal performance in compact layouts.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar voltage supervisor applications.

Compared with TPS389025DSET, TPS389725DSER adds watchdog capability at higher quiescent current and complexity, while MAX6325EUR+T sacrifices adjustability and MR support for lower cost and marginally lower IQ - making TPS389025DSET optimal for flexible, low-power, manually controllable supervision.

Availability

TPS389025DSET is available at Aetrix Electronics and suitable for microcontroller power sequencing, FPGA configuration integrity, battery-powered sensor nodes, and industrial PLC I/O modules requiring stable component supply with guaranteed long-term manufacturability.

Supply support for TPS389025DSET includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader delivering analog and embedded processing solutions, with over 90 years of innovation in power management, signal chain, and real-time control technologies.

The TPS3890 family was engineered specifically for ultra-low-power, high-accuracy voltage supervision in space-constrained embedded systems - targeting applications where traditional supervisors consume too much current or lack sufficient threshold stability over temperature.

FAQ

What is the exact threshold voltage of the TPS389025DSET and how does it vary with temperature?

The TPS389025DSET has a factory-set negative threshold voltage (VITN) of 2.40 V and positive threshold (VITP) of 2.414 V at 25°C. Over –40°C to +125°C, threshold accuracy is guaranteed within ±1% - meaning VITN remains between 2.376 V and 2.424 V across the full temperature range. This is verified by TI's production test data showing ±0.75% typical deviation, as shown in Figure 2 of the TPS389025DSET datasheet.

How do I calculate the CT capacitor value needed for a specific reset delay time with the TPS389025DSET?

Use the formula tPD(r) = CCT × 1.07 + 25 µs (nominal), where tPD(r) is the desired rising-edge RESET delay in seconds and CCT is the CT capacitor value in farads. For example, a 100 ms delay requires CCT ≈ 93.2 nF. To ensure worst-case timing across temperature and process variation, select a capacitor with ±10% tolerance and low leakage (e.g., X7R ceramic), and verify with the TPS389025DSET's ICT = 1.15 µA and VCT = 1.23 V specifications.

Can the TPS389025DSET monitor a voltage rail higher than its VDD supply voltage?

Yes. The SENSE pin of the TPS389025DSET accepts input voltages from 0 V to 5.5 V independently of the VDD supply voltage (1.5 V to 5.5 V). This allows monitoring of higher-voltage rails - such as a 3.3 V I/O supply - while powering the TPS389025DSET from a lower 1.8 V domain. No level-shifting circuitry is required, simplifying design and reducing component count.

What is the maximum sink current capability of the TPS389025DSET RESET output?

The TPS389025DSET RESET output is an open-drain NMOS device rated for a maximum sink current of 20 mA. At IRESET = 0.4 mA and VDD ≥ 1.5 V, VOL is guaranteed ≤ 0.25 V. For higher currents (e.g., 2 mA at VDD ≥ 2.7 V), VOL remains ≤ 0.25 V. This ensures robust drive strength for standard logic inputs and compatibility with common pull-up resistor values (10 kΩ–1 MΩ).

Does the TPS389025DSET require an external pull-up resistor on the RESET pin, and what value should be used?

Yes - the TPS389025DSET RESET pin is open-drain and requires an external pull-up resistor to define the logic-high state. Recommended values range from 10 kΩ to 1 MΩ, selected based on rise time requirements and power budget. A 100-kΩ resistor provides fast edges (<1 µs with 10 pF load) and draws only 33 µA from a 3.3 V rail, while a 1-MΩ resistor minimizes current (3.3 µA) for ultra-low-power applications.