Texas Instruments TPS389033DSET

Overview

TPS389033DSET from Texas Instruments is a precision voltage supervisor IC that monitors 3.3-V system rails, asserts an open-drain RESET signal when SENSE voltage falls below 3.17 V (VITN), and provides user-programmable reset delay up to 30 s via external capacitor on CT pin. It delivers 1% threshold accuracy over –40°C to +125°C, draws only 2.1 µA typical quiescent current, and operates from 1.5-V to 5.5-V supply - ideal for battery-powered microcontroller power sequencing in space-constrained embedded systems.

For engineers reviewing the TPS389033DSET datasheet, TPS389033DSET pinout, TPS389033DSET application, or TPS389033DSET equivalent, key selection considerations include its fixed 3.3-V monitoring threshold, programmable delay timing (25 µs–30 s), open-drain RESET output compatibility with diverse logic families, and WSON-6 package suitability for high-density PCB layouts.

Technical Context

The TPS389033DSET implements a precision bandgap reference and comparator architecture to achieve ±1% VITN accuracy across temperature. Its internal CT pin current source (1.15 µA nominal) charges an external capacitor to set the rising-edge RESET deassertion delay, while built-in hysteresis (0.575% typ.) prevents chatter during rail recovery.

It supports dual-trigger reset assertion: voltage drop below 3.17 V on SENSE or logic-low pulse on MR input. RESET remains asserted for the full programmed delay after both conditions clear, ensuring reliable microcontroller initialization. The device enters undefined state only when VDD drops below 0.8 V (VPOR), and operates fully within 1.5–5.5 V supply range.

Key Specifications

Pinout & Package

TPS389033DSET is housed in a 1.5-mm × 1.5-mm, 6-pin WSON (DSE) package with wettable flanks, optimized for automated optical inspection and thermal performance in compact designs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar voltage supervisor applications.

Compared with TPS389033DSET, TPS389733DSET adds watchdog capability at higher complexity and cost, while MAX6326UT33+T trades programmability for lower quiescent current and fixed timing - making TPS389033DSET the optimal balance of precision, flexibility, and power efficiency for modern embedded systems.

Availability

TPS389033DSET is available at Aetrix Electronics and suitable for microcontroller power sequencing, FPGA configuration monitoring, solid-state drive power management, industrial PLC I/O modules, and battery-powered edge sensor nodes requiring stable component supply and long-term lifecycle support.

Supply support for TPS389033DSET includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and power management technologies, with leadership in high-reliability industrial and automotive-grade components.

The TPS3890 family is designed specifically for precision power-supply monitoring in space- and power-constrained systems, targeting applications demanding ultra-low IQ, programmable timing, and guaranteed reset behavior across extended temperature ranges.

FAQ

What is the exact negative threshold voltage (VITN) for TPS389033DSET?

The TPS389033DSET has a fixed negative threshold voltage (VITN) of 3.17 V, with ±1% maximum accuracy over –40°C to +125°C. This value is factory-trimmed and specified in the Electrical Characteristics table of the SLVSD65A datasheet. The corresponding positive threshold (VITP) is 3.189 V, providing 0.575% hysteresis to prevent oscillation during rail recovery. These thresholds are guaranteed for all units in the production lot.

How do I calculate the CT capacitor value needed for a 100-ms reset delay with TPS389033DSET?

Use the formula t_PD(r) = C_CT × 1.07 + 25 µs. For 100 ms (100,000 µs), solve: C_CT = (100,000 – 25) ÷ 1.07 ≈ 93,458 pF → 93.5 nF. Select a standard 100-nF ceramic capacitor (X7R, ±10% tolerance) with low leakage. Place it close to the CT pin with short traces to minimize parasitic capacitance, as board leakage can reduce effective delay time.

Can TPS389033DSET monitor a 3.3-V rail while powered from a 1.8-V supply?

No - TPS389033DSET requires VDD ≥1.5 V to operate, but its SENSE input is rail-to-rail (0–5.5 V), so it can monitor a 3.3-V rail while powered from 1.8 V. However, the RESET output is open-drain and must be pulled up to the target logic voltage (e.g., 3.3 V). Ensure the pullup resistor value (e.g., 47 kΩ) satisfies VOL ≤0.25 V at 0.4 mA sink current per the datasheet, even with 1.8-V VDD.

What is the minimum recommended pullup resistor value for the RESET pin of TPS389033DSET?

The minimum pullup resistor is determined by VOL specification: at I_RESET = 0.4 mA and VDD ≥1.5 V, VOL ≤0.25 V. Using Ohm's Law, R_PU(min) = (V_PULLUP – VOL) ÷ I_RESET. For a 3.3-V pullup, R_PU(min) = (3.3 – 0.25) ÷ 0.0004 = 7.6 kΩ. TI recommends 10 kΩ–100 kΩ for robust noise immunity and low power; avoid values <5 kΩ to prevent excessive current during RESET assertion.

Does TPS389033DSET support manual reset (MR) debouncing, and what is the minimum MR pulse width?

TPS389033DSET provides 100 ns MR pin glitch immunity at VDD = 5.5 V, meaning pulses shorter than this are ignored. The minimum valid MR pulse width to guarantee RESET assertion is 1 µs (t_MRW). For mechanical button interfaces, external RC filtering (e.g., 100 kΩ + 100 nF = 10 µs time constant) is recommended to suppress contact bounce, as the device itself does not include internal digital debouncing logic.