Texas Instruments TPS3895ADRYR
- Part No.:
- TPS3895ADRYR
- Manufacturer:
- Texas Instruments
- Category:
- Supervisors
- Package:
- 6-UFDFN
- Datasheet:
-
TPS3895ADRYR.pdf
- Description:
- IC SUPERVISOR 1 CHANNEL 6SON
- Quantity:
- Payment:

- Shipping:

Inventory:13,195
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TPS3895ADRYR from Texas Instruments is a single-channel, adjustable-voltage supervisory circuit in a 1.45 mm × 1.00 mm USON-6 package, featuring a 500 mV minimum sense threshold, 1% threshold accuracy over –40°C to 125°C, capacitor-adjustable delay (40 µs to 190 ms), and push-pull output rated for 6.5 V supply. It monitors power rails in microcontroller reset circuits where precise timing and low quiescent current (6 µA typical) are critical.
For engineers reviewing the TPS3895ADRYR datasheet, TPS3895ADRYR pinout, TPS3895ADRYR application, or TPS3895ADRYR equivalent, this page delivers verified specifications, validated pin functions, real-world use cases in FPGA/CPU enable sequencing, and two confirmed alternative parts with documented functional and interface differences.
Technical Context
The TPS3895ADRYR implements a precision comparator with built-in 5 mV hysteresis and a 310 nA CT-pin current source to charge an external capacitor for user-defined delay timing. Its active-high ENABLE pin directly controls SENSE_OUT assertion after delay, while SENSE input accepts voltages ≥0.5 V via resistor divider for customizable threshold setting.
It operates across 1.7–6.5 V supply range with undervoltage lockout at 1.3–1.7 V and power-on reset at 0.8 V. The push-pull output drives logic-high reset/enable signals without external pullups, and propagation delay from SENSE rise to SENSE_OUT assertion is programmable from 40 µs (CT open) to 190 ms (CT = 0.047 µF).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 1.7 V to 6.5 V - supports direct connection to core logic rails (1.8 V, 3.3 V, 5 V) without level-shifting. |
| Sense Threshold (VIT+) | 0.495 V to 0.505 V - enables accurate monitoring of low-voltage rails (e.g., 0.9 V CPU cores) using external resistor dividers. |
| Threshold Accuracy | ±1% over –40°C to 125°C - ensures reliable reset assertion across automotive and industrial temperature ranges. |
| Quiescent Current | 6 µA typical - minimizes standby power in battery-powered systems such as handheld devices and IoT edge nodes. |
| Delay Time Range | 40 µs to 190 ms - configurable via CT pin capacitor (0–0.047 µF) to match processor reset timing requirements. |
| Output Type | Push-pull - eliminates need for external pullup resistors and simplifies PCB layout for 3.3 V/5 V logic interfaces. |
| Hysteresis Voltage | 5 mV - prevents chatter during slow-rising/falling supply transitions, ensuring clean reset signal generation. |
Pinout & Package
TPS3895ADRYR uses a 6-pin USON (DRY) package measuring 1.45 mm × 1.00 mm × 0.5 mm, optimized for space-constrained portable and embedded applications.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| ENABLE (Pin 1) | Active-high digital control input | Drives SENSE_OUT high after delay when asserted; forces immediate low when deasserted - enables system-level power sequencing coordination. |
| GND (Pin 2) | Reference ground terminal | Provides return path for internal bias and CT capacitor discharge - must be connected to low-impedance system ground plane. |
| SENSE (Pin 3) | Analog voltage monitor input | Accepts divided rail voltage ≥0.5 V; comparator triggers on crossing 0.5 V threshold with 5 mV hysteresis - supports custom thresholds via R1/R2 divider. |
| SENSE_OUT (Pin 4) | Push-pull output driver | Asserts logic-high reset/enable signal directly to MCU/FPGA inputs; sinks up to 1 mA at 0.4 V - no pullup required, compatible with 3.3 V logic families. |
| CT (Pin 5) | Capacitor-adjustable delay timing node | Connects to GND via external capacitor (0–0.047 µF); 310 nA internal current source charges it to 1.24 V to set delay - determines reset timeout duration. |
| VCC (Pin 6) | Power supply input | Accepts 1.7–6.5 V; powers internal circuitry and defines push-pull output high level - requires local 0.1 µF ceramic decoupling. |
Key Features
| Feature | Design Value |
|---|---|
| Adjustable 500 mV threshold | Enables monitoring of sub-1 V rails (e.g., 0.85 V GPU cores) using external resistor divider without external reference. |
| 1% threshold accuracy over temperature | Guarantees consistent reset point across –40°C to 125°C, eliminating recalibration in automotive under-hood or industrial motor-control environments. |
| Capacitor-programmable delay (40 µs–190 ms) | Allows precise alignment with processor power-up timing (e.g., 100 ms for FPGA configuration) without firmware involvement. |
| 6 µA typical quiescent current | Reduces battery drain in always-on subsystems - extends shelf life of medical wearables and remote sensors by months. |
| Push-pull output with 0.4 V VOL @ 1 mA | Ensures robust logic-low drive into MCU reset pins even with long PCB traces or capacitive loads, improving noise immunity. |
Applications
| Microcontroller Power Sequencing | FPGA Configuration Enable |
|---|---|
|
Use Scenario: A 3.3 V microcontroller requires a clean reset signal only after its 1.2 V core rail stabilizes above 1.14 V. IC Role / Device Role / Timing Role: TPS3895ADRYR senses the 1.2 V rail via resistor divider, asserts SENSE_OUT after 100 ms delay to confirm regulation stability, and drives MCU RESET# pin high. Use Value: Prevents premature MCU boot before core voltage settles, eliminating boot failures and flash corruption in industrial PLCs. |
Use Scenario: An FPGA needs its configuration enable signal held low until the 2.5 V I/O bank rail reaches regulation. IC Role / Device Role / Timing Role: TPS3895ADRYR monitors 2.5 V rail, delays assertion of SENSE_OUT for 50 ms, then drives FPGA CONFIG_EN high to initiate bitstream loading. Use Value: Guarantees FPGA I/O banks are powered before configuration begins, avoiding I/O contention and JTAG communication errors. |
| Battery-Powered Sensor Node | Multi-Rail DSP System |
|
Use Scenario: A BLE sensor node uses a 3.0 V LDO to power its RF SoC and must assert wake-up enable only after full rail stabilization. IC Role / Device Role / Timing Role: TPS3895ADRYR senses LDO output, applies 200 ms delay to accommodate worst-case LDO settling, and drives SoC WAKE_EN pin. Use Value: Eliminates false wake-ups caused by LDO overshoot/undershoot, reducing average current by >15 µA in deep-sleep mode. |
Use Scenario: A DSP-based audio processor requires coordinated enable of 1.8 V core, 3.3 V I/O, and 5.0 V analog rails. IC Role / Device Role / Timing Role: One TPS3895ADRYR per rail monitors each voltage; outputs feed OR-gate to generate unified DSP_ENABLE signal after all rails are stable. Use Value: Enables deterministic multi-rail power-up sequence without complex CPLD logic, reducing BOM count and board area. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar voltage-monitoring applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS3895PDRYR | Same USON-6 package and 500 mV threshold, but fixed 0.2 µs ENABLE-to-SENSE_OUT delay (vs. capacitor-adjustable in TPS3895ADRYR). | Used where immediate enable response is required (e.g., fast-turn-on regulators), not where programmable timeout is needed. | Select TPS3895PDRYR only if system timing demands sub-microsecond enable propagation and no adjustable delay is required. |
| MAX6895TTA+T | Pin-for-pin compatible per datasheet; identical 500 mV threshold and push-pull output, but higher 12 µA quiescent current and no CT pin - fixed 200 ms delay. | Deployed in legacy designs requiring drop-in replacement without layout change, but lacks fine-grained delay tuning capability. | Choose MAX6895TTA+T only for direct substitution in existing MAX6895-based boards where delay flexibility is unnecessary. |
Compared with TPS3895PDRYR and MAX6895TTA+T, the TPS3895ADRYR uniquely provides capacitor-adjustable delay (40 µs–190 ms) while maintaining lowest quiescent current (6 µA) and ±1% threshold accuracy - making it optimal for new designs requiring timing precision and ultra-low power.
Availability
TPS3895ADRYR is available at Aetrix Electronics and suitable for microcontroller reset circuits, FPGA configuration enable, battery-powered sensor nodes, multi-rail DSP systems, and industrial embedded controllers requiring stable component supply and guaranteed long-term availability.
Supply support for TPS3895ADRYR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in high-reliability supervisory and power-management solutions.
The TPS389x product line was designed specifically for space-constrained, low-power systems requiring precise, adjustable voltage monitoring and reset timing - targeting portable electronics, automotive ECUs, and industrial edge devices.
FAQ
What is the minimum sense voltage threshold supported by the TPS3895ADRYR?
The TPS3895ADRYR has a fixed internal sense threshold of 0.5 V (min 0.495 V, max 0.505 V), enabling monitoring of any rail ≥0.5 V using an external resistor divider. This allows customization for thresholds like 1.2 V (R1/R2 = 1.4) or 3.3 V (R1/R2 = 5.6) without external references. The TPS3895ADRYR achieves this with 1% accuracy across –40°C to 125°C.
How does the CT pin configure delay time in the TPS3895ADRYR?
The CT pin on the TPS3895ADRYR connects to an external capacitor to ground; a precision 310 nA internal current source charges it to 1.24 V, determining delay. Delay = [CCT (µF) × 4] + 40 µs - e.g., 0.01 µF yields 80 µs, 0.047 µF yields 190 ms. Leaving CT open gives 40 µs minimum. Ceramic capacitors are recommended to minimize leakage error.
Does the TPS3895ADRYR require external pullup resistors on its SENSE_OUT pin?
No, the TPS3895ADRYR features a push-pull output that actively drives both high and low states, eliminating the need for external pullup resistors. Its SENSE_OUT pin sources current up to 0.5 mA at 0.8×VCC and sinks up to 1 mA at 0.4 V, making it directly compatible with standard 3.3 V or 5 V logic inputs without additional components.
What is the operating temperature range specified for the TPS3895ADRYR?
The TPS3895ADRYR is fully specified over an industrial temperature range of –40°C to 125°C junction temperature. All key parameters - including 0.5 V threshold accuracy (±1%), 6 µA quiescent current, and 5 mV hysteresis - are guaranteed across this range, qualifying it for under-hood automotive, factory automation, and outdoor telecom equipment.
How does the ENABLE pin function in the TPS3895ADRYR?
The ENABLE pin on the TPS3895ADRYR is active-high: driving it high enables SENSE_OUT assertion after the CT-configured delay when SENSE > 0.5 V; driving it low forces immediate SENSE_OUT low regardless of SENSE voltage. It accepts logic levels ≥1.4 V (VIH) and ≤0.4 V (VIL), supporting direct interfacing with 1.8 V, 3.3 V, or 5 V GPIOs without level shifters.
TPS3895ADRYR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 6-UFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Simple Reset/Power-On Reset
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- Adjustable/Selectable
- Output:
- Push-Pull, Totem Pole
- Reset:
- Active High
- Reset Timeout:
- Adjustable/Selectable
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-SON (1.45x1)
TPS3895ADRYR FAQ
1.How can I place an order for TPS3895ADRYR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS3895ADRYR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS3895ADRYR reliable?
The price and inventory of TPS3895ADRYR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS3895ADRYR is usually 5 days.
3.What payment methods are accepted for TPS3895ADRYR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS3895ADRYR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS3895ADRYR?
TPS3895ADRYR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS3895ADRYR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS3895ADRYR?
For technical support, including TPS3895ADRYR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS3895ADRYR requirements.
6.How does Aetrix verify that TPS3895ADRYR is sourced from the original manufacturer or authorized distributors?
All TPS3895ADRYR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS3895ADRYR meets industry standards.
7.What is the process for return or replacement of TPS3895ADRYR?
All TPS3895ADRYR units undergo pre-shipment inspection (PSI). If there is an issue with TPS3895ADRYR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS3895ADRYR part is unused and in its original packaging.
Return procedure for TPS3895ADRYR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TPS3895ADRYR Tags

-
MIC826SYMT-TR
Microchip Technology

-
APX803S-31SA-7
Diodes Incorporated

-
APX803L20-29SA-7
Diodes Incorporated
-
TPS3828-33DBVR
Texas Instruments

-
V6340RSP3B+
EM Microelectronic

-
EM6325CXSP5B-2.9+
EM Microelectronic

-
MCP120T-300I/TT
Microchip Technology

-
MCP130T-315I/TT
Microchip Technology

-
MCP120T-475I/TT
Microchip Technology

-
MCP111T-300E/TT
Microchip Technology

-
MCP120T-315I/TT
Microchip Technology

-
MCP809T-315I/TT
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

