Texas Instruments TPS3895ADRYT

Overview

TPS3895ADRYT from Texas Instruments is a single-channel, adjustable-voltage supervisory circuit in a 1.45 mm × 1.00 mm USON-6 package. It monitors supply rails ≥500 mV with 1% threshold accuracy over –40°C to 125°C, supports capacitor-adjustable delay (40 µs to 190 ms), features push-pull output rated for 6.5 V supply, and delivers 6 µA typical quiescent current - used for reliable power-on reset assertion in microcontroller and FPGA enable sequencing.

For engineers reviewing the TPS3895ADRYT datasheet, TPS3895ADRYT pinout, TPS3895ADRYT application, or TPS3895ADRYT equivalent, key selection criteria include its 0.5 V fixed internal threshold (adjustable via external resistor divider), active-high ENABLE logic, 16 µs fast deassertion delay, open-drain/push-pull output configurability across family variants, and compatibility with low-noise, battery-sensitive embedded systems requiring precise voltage monitoring and timing control.

Technical Context

The TPS3895ADRYT implements a precision comparator with 5 mV hysteresis and 0.5 V reference to detect SENSE pin voltage crossing above V_IT+; threshold accuracy remains within ±1% across full temperature range. Its CT pin integrates a 310 nA current source charging an external capacitor to generate programmable assertion delay per t_pd(r) = [C_CT (µF) × 4] + 40 µs.

It operates from 1.7 V to 6.5 V supply, includes undervoltage lockout (UVLO) at 1.3–1.7 V, and guarantees sub-1 µA leakage on SENSE and ENABLE pins. The push-pull output drives high to V_CC and sinks ≤0.3 V at 0.5 mA, enabling direct interface with 1.8 V/3.3 V logic without pull-up resistors.

Key Specifications

Pinout & Package

TPS3895ADRYT uses a 6-pin USON (DRY) package measuring 1.45 mm × 1.00 mm × 0.5 mm, optimized for space-constrained portable and industrial PCB layouts.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar voltage monitor applications.

Compared with TPS3895PDRYT, the TPS3895ADRYT provides design flexibility through capacitor-adjustable delay at the cost of slightly longer minimum assertion time; versus MAX6895TTA+T, it delivers 50% lower quiescent current and full delay programmability, making it superior for energy-constrained and timing-critical new designs.

Availability

TPS3895ADRYT is available at Aetrix Electronics and suitable for microcontroller reset sequencing, FPGA configuration enable, battery-powered sensor node supervision, multi-rail DSP power management, and industrial embedded control requiring stable component supply and long-term lifecycle support.

Supply support for TPS3895ADRYT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader delivering analog, embedded processing, and connectivity solutions for industrial, automotive, and consumer markets.

The TPS389x product line was designed specifically for ultra-small-footprint, low-quiescent-current voltage supervision in space- and power-constrained portable, medical, and industrial electronics - emphasizing precision threshold accuracy, flexible timing, and robust noise immunity.

FAQ

What is the minimum supply voltage required for TPS3895ADRYT to operate correctly?

The TPS3895ADRYT requires a minimum supply voltage of 1.7 V to guarantee functional operation, with undervoltage lockout (UVLO) activating below 1.3–1.7 V. Below 1.7 V, the output becomes undefined, and the device enters a non-operational state. For reliable power-on reset generation, V_CC must exceed 1.7 V for at least 50 µs plus propagation delay before the output reaches its correct asserted state. This specification is confirmed in Section 7.3 of the SBVS172B datasheet.

Can TPS3895ADRYT monitor a 1.2 V rail, and how is the threshold set?

Yes, TPS3895ADRYT can monitor a 1.2 V rail using an external resistor divider on the SENSE pin. With its fixed 0.5 V internal threshold, a 1.2 V rail requires a divider ratio of (1.2 V / 0.5 V) – 1 = 1.4, achieved with R1 = 140 kΩ and R2 = 100 kΩ. This configuration ensures the SENSE pin sees exactly 0.5 V when the rail reaches 1.2 V. The device's <15 nA input current introduces negligible error, and the 1% threshold accuracy holds across temperature. Equation 1 in Section 8.3.1 confirms this calculation method.

What is the maximum capacitor value supported on the CT pin of TPS3895ADRYT?

The CT pin of TPS3895ADRYT supports capacitors up to 0.047 µF (47 nF), yielding a maximum delay of 190 ms per the formula t_pd(r) = [C_CT (µF) × 4] + 40 µs. Larger capacitors increase delay linearly but reduce timing accuracy due to stray capacitance and leakage effects. The datasheet specifies 47 nF as the maximum tested value for guaranteed 190 ms delay; beyond this, timing deviation increases significantly. Ceramic capacitors are strongly recommended for low leakage and stability across temperature.

Does TPS3895ADRYT require external pull-up resistors on its SENSE_OUT pin?

No, TPS3895ADRYT does not require external pull-up resistors because it features a push-pull output stage. Its SENSE_OUT pin actively drives high to V_CC and low to <0.3 V at 0.5 mA, eliminating dependency on external components for logic-level translation. This contrasts with open-drain variants like TPS3897ADRYT, which mandate pull-ups. The push-pull architecture reduces BOM count and board area - a key advantage confirmed in Section 1 (Features) and Pin Functions table of the SBVS172B datasheet.

How does the hysteresis of TPS3895ADRYT prevent false resets during supply droop?

The TPS3895ADRYT incorporates 5 mV of built-in hysteresis between its rising threshold (V_IT+) and falling threshold (V_IT+ – V_hys). When the monitored rail rises above 0.5 V, SENSE_OUT asserts; it only deasserts when the rail falls below 0.495 V. This 5 mV window prevents oscillation during marginal or noisy supply conditions - such as brief load-induced droops - ensuring a single, clean reset event. Figure 8 in the datasheet validates this hysteresis stability across temperature and supply voltage.