Texas Instruments TPS3898ADRYR

Overview

TPS3898ADRYR from Texas Instruments is an ultra-small, active-low enable, open-drain voltage supervisor IC designed for precision power-rail monitoring in space-constrained systems. It features a 500 mV adjustable threshold (±1% over –40°C to 125°C), capacitor-programmable delay (40 µs to 190 ms), 6 µA typical quiescent current, and operates from 1.7 V to 6.5 V supply. It is used in FPGA reset sequencing, microcontroller brownout detection, and battery-powered device power-up validation.

For engineers reviewing the TPS3898ADRYR datasheet, TPS3898ADRYR pinout, TPS3898ADRYR application, or TPS3898ADRYR equivalent, key selection criteria include its active-low ENABLE logic, open-drain SENSE_OUT rated to 18 V, USON-6 (1.45 mm × 1.00 mm) package, temperature-stable 1% threshold accuracy, and capacitor-adjustable delay timing - all critical for low-power, high-reliability embedded supervision.

Technical Context

The TPS3898ADRYR implements a precision comparator with built-in 5 mV hysteresis (V_IT+ − V_HYS) referenced to a stable 500 mV internal threshold, enabling accurate monitoring of user-defined voltages via external resistor dividers. Its CT pin integrates a 310 nA precision current source that charges an external capacitor to set delay time per t_pd(r) = [C_CT (µF) × 4] + 40 µs.

It uses active-low ENABLE logic: asserting ENABLE (driving high) initiates output assertion only after the CT-delayed interval when SENSE > V_IT+; deasserting ENABLE (driving low) forces immediate SENSE_OUT high. The open-drain output supports level-shifting up to 18 V independent of V_CC, requiring external pull-up.

Key Specifications

Pinout & Package

TPS3898ADRYR is housed in a 6-pin USON (DRY) package measuring 1.45 mm × 1.00 mm × 0.5 mm, optimized for ultra-dense PCB layouts and automated assembly.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar voltage supervisor applications.

Compared with TPS3898PDRYR and MAX6898ATT+T, the TPS3898ADRYR uniquely balances 1% threshold accuracy, capacitor-tunable delay, and 6 µA IQ in a 1.45 mm × 1.00 mm package - making it optimal for applications demanding both precision and flexibility in compact designs.

Availability

TPS3898ADRYR is available at Aetrix Electronics and suitable for FPGA configuration monitoring, microcontroller brownout protection, and battery-powered system shutdown requiring stable component supply across automotive, industrial, and portable electronics programs.

Supply support for TPS3898ADRYR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader delivering analog and embedded processing solutions, with deep expertise in power management, signal chain, and real-time control ICs.

The TPS389x family was designed specifically for ultra-compact, low-power voltage supervision in space- and energy-constrained systems - targeting portable electronics, automotive ECUs, and industrial edge nodes where board area and standby current are critical.

FAQ

What is the minimum detectable input voltage for TPS3898ADRYR?

The TPS3898ADRYR has a fixed internal reference of 500 mV, which serves as the base threshold. Using an external resistor divider on the SENSE pin, it can monitor any input voltage ≥500 mV - including 0.8 V, 1.2 V, 3.3 V, or 5 V rails. The actual monitored voltage is calculated as V_IN = (1 + R1/R2) × 0.5 V, where R1 and R2 form the divider network feeding the SENSE pin. This makes TPS3898ADRYR applicable to modern low-voltage SoCs and FPGAs.

How does the CT pin set the delay time in TPS3898ADRYR?

The CT pin in TPS3898ADRYR connects to an internal 310 nA precision current source. When a capacitor (C_CT) is placed between CT and GND, the current source charges it until the voltage reaches ~1.24 V, triggering SENSE_OUT assertion. Delay time follows t_pd(r) = [C_CT (µF) × 4] + 40 µs - e.g., 0.047 µF yields ~190 ms. Leaving CT open gives a fixed 40 µs delay. Ceramic capacitors are recommended to minimize leakage-induced error.

Can TPS3898ADRYR drive a 5 V microcontroller reset pin directly?

Yes - the TPS3898ADRYR's open-drain SENSE_OUT is rated to 18 V and requires only an external pull-up resistor to the target logic rail (e.g., 5 V). When asserted, it pulls the reset line low; when deasserted, the pull-up returns it high. No level shifter is needed. Ensure the pull-up value limits sink current to ≤1 mA (e.g., ≥5 kΩ for 5 V), matching the device's electrical characteristics.

What is the role of the ENABLE pin in TPS3898ADRYR?

The ENABLE pin in TPS3898ADRYR is active-low: driving it high enables supervision (output asserts after CT delay when SENSE > V_IT+); driving it low forces immediate SENSE_OUT high, overriding all other conditions. This allows external control - e.g., holding a processor in reset until firmware initializes peripherals. Its 0.4 V max V_IL and 1.4 V min V_IH ensure compatibility with 1.8 V and higher logic families.

Does TPS3898ADRYR support operation below 1.7 V?

No - the absolute minimum operating supply voltage for TPS3898ADRYR is 1.7 V per the Recommended Operating Conditions table. Below this, the internal circuitry cannot guarantee correct behavior. The device includes undervoltage lockout (UVLO) at 1.3 V (typical), which deasserts output when V_CC falls below that level. For sub-1.7 V applications, consider alternative supervisors like TPS3808G or discrete solutions.