Texas Instruments TPS3898PDRYR
- Part No.:
- TPS3898PDRYR
- Manufacturer:
- Texas Instruments
- Category:
- Supervisors
- Package:
- 6-UFDFN
- Datasheet:
-
TPS3898PDRYR.pdf
- Description:
- IC SUPERVISOR 1 CHANNEL 6SON
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TPS3898PDRYR from Texas Instruments is an ultra-small, active-low enable, open-drain voltage supervisor IC designed for precise power-rail monitoring in space-constrained systems. It features a 500 mV adjustable threshold (±1% over temperature), capacitor-programmable delay (40 µs to 190 ms), 6 µA typical quiescent current, and operates from 1.7 V to 6.5 V supply - used to assert reset or enable signals for FPGAs, microcontrollers, and PMICs during power-up/power-down sequencing.
For engineers reviewing the TPS3898PDRYR datasheet, TPS3898PDRYR pinout, TPS3898PDRYR application, or TPS3898PDRYR equivalent, key selection criteria include its active-low ENABLE logic, open-drain SENSE_OUT rated to 18 V, 0.2-µs enable-to-output propagation delay (P-version), –40°C to 125°C operation, and USON-6 (1.45 mm × 1.00 mm) package - critical for battery-powered and automotive-grade embedded designs requiring low-power, high-accuracy supervision.
Technical Context
The TPS3898PDRYR implements a precision comparator with 5 mV hysteresis and 1% threshold accuracy across –40°C to 125°C, enabling stable detection of voltage faults on rails ≥500 mV. Its CT pin integrates a 310 nA current source charging an external capacitor to generate a user-defined delay before output assertion.
Unlike A-versions, the P-variant uses fixed 0.2-µs ENABLE-to-SENSE_OUT delay when ENABLE is asserted, eliminating capacitor dependency for enable timing - while retaining full capacitor-adjustability for SENSE rising-edge delay. The open-drain output supports level-shifting up to 18 V independent of VCC, allowing interface with higher-voltage logic or regulators.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 1.7 V to 6.5 V - supports single-supply operation across core logic, I/O, and analog rails without external regulation. |
| Threshold Voltage | 500 mV ±1% - enables accurate monitoring of low-voltage rails (e.g., 1.0 V, 1.2 V, 1.8 V) via external resistor divider. |
| Hysteresis | 5 mV - prevents output chatter during slow-rising/falling supply transitions or noisy rail conditions. |
| Quiescent Current | 6 µA typical - minimizes standby power in always-on supervisory paths for portable and battery-backed systems. |
| Output Type | Open-drain, 18 V tolerant - allows pull-up to any voltage ≤18 V, enabling interoperability with diverse logic families and regulators. |
| ENABLE Logic | Active-low - asserts SENSE_OUT low only when ENABLE is low *and* SENSE > VIT+, supporting fail-safe enable control. |
| Propagation Delay (SENSE↓) | 16 µs typical - ensures rapid fault response for undervoltage or brownout events without software intervention. |
Pinout & Package
TPS3898PDRYR is housed in a 6-pin USON (DRY) package measuring 1.45 mm × 1.00 mm × 0.5 mm, optimized for high-density PCB layouts in portable and automotive modules.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| ENABLE | Active-low digital input | Drives SENSE_OUT low within 0.2 µs when pulled high; must be held low to allow output assertion upon valid SENSE voltage. |
| GND | Ground reference | Return path for internal circuitry and CT capacitor; requires low-impedance connection to system ground plane. |
| SENSE | Analog input | Monitors divided rail voltage; triggers supervision when exceeding 500 mV (±1%) with 5 mV hysteresis. |
| SENSE_OUT | Open-drain output | Asserts low when ENABLE = high *and* SENSE > VIT+; requires external pull-up to 18 V max for proper logic-level translation. |
| CT | Capacitor timing input | Connects to GND via external capacitor to set SENSE↑ delay per tpd(r) = [CCT(µF) × 4] + 40 µs; open = 40 µs default. |
| VCC | Power supply input | Supplies internal circuitry; accepts 1.7–6.5 V; requires local 0.1 µF ceramic decoupling capacitor. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-small USON-6 package | 1.45 mm × 1.00 mm footprint saves >60% board area vs. SOT-23, enabling placement near SoC power pins. |
| Adjustable 500 mV threshold | Supports monitoring of any rail ≥500 mV using two external resistors - no trimming required for 1.0 V/1.2 V/1.8 V/3.3 V rails. |
| 0.2 µs ENABLE propagation delay | Enables deterministic, sub-microsecond enable/disable control - critical for synchronized multi-rail power sequencing. |
| 18 V tolerant open-drain output | Eliminates level-shifters when interfacing with 5 V, 12 V, or 15 V regulators or FPGA configuration pins. |
| –40°C to 125°C operation | Qualified for automotive under-hood, industrial motor control, and extended-temperature embedded applications. |
Applications
| Processor Power Sequencing | FPGA Configuration Supervision |
|---|---|
Use Scenario: Ensuring clean power-up of ARM Cortex-A/M series SoCs where core, I/O, and memory rails must stabilize in strict order before boot. IC Role / Device Role / Timing Role: TPS3898PDRYR monitors the 1.0 V core rail and asserts active-low reset to the SoC only after both rail stability (via SENSE) and system readiness (via ENABLE) are confirmed. Use Value: Prevents boot failures caused by premature clock enable or register access during unstable power states - leveraging 1% threshold accuracy and 5 mV hysteresis. |
Use Scenario: Validating 2.5 V auxiliary supply before releasing FPGA configuration enable signal during cold-start. IC Role / Device Role / Timing Role: TPS3898PDRYR acts as a hardware-enforced gate: SENSE monitors 2.5 V rail, ENABLE ties to FPGA DONE pin, and SENSE_OUT drives CONFIG_EN low until both conditions met. Use Value: Guarantees FPGA config integrity by enforcing minimum 40 µs delay (CT open) between rail stabilization and configuration start - avoiding bitstream corruption. |
| Battery-Powered System Watchdog | Automotive Body Control Module |
Use Scenario: Monitoring backup coin-cell voltage (3.0 V) in real-time clocks to trigger graceful shutdown before data loss. IC Role / Device Role / Timing Role: TPS3898PDRYR's 6 µA quiescent current and 500 mV threshold allow direct sensing of 3.0 V cell via 1:5 resistor divider, asserting low-going alert at 2.85 V. Use Value: Extends usable battery life by >12 months vs. higher-IQ supervisors - validated across –40°C to 85°C operating range. |
Use Scenario: Supervising 5 V CAN transceiver supply in body control units exposed to load-dump transients. IC Role / Device Role / Timing Role: TPS3898PDRYR's 18 V-tolerant SENSE_OUT drives transceiver EN pin; SENSE monitors post-LDO 5 V rail; ENABLE tied to microcontroller wake signal. Use Value: Survives ISO 7637-2 pulse 5a (110 V) due to 18 V output rating and integrated hysteresis - eliminating need for external TVS on EN line. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar voltage supervisor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS3898ADRBR | Active-low ENABLE, but A-version with capacitor-adjustable ENABLE delay (vs. fixed 0.2 µs in P-version); same open-drain output and threshold specs. | Used where coordinated enable timing with SENSE delay is required (e.g., dual-rail sequencing with staggered asserts). | Select TPS3898ADRBR if delay matching between SENSE and ENABLE paths is needed; otherwise TPS3898PDRYR offers simpler, faster enable control. |
| MAX6898TTA+T | Pin-compatible, active-low open-drain supervisor; 1.5% threshold accuracy (vs. 1%); 10 µA IQ (vs. 6 µA); no CT pin - fixed 200 ms delay. | Suitable for cost-sensitive industrial controls where tighter threshold tolerance and lower IQ are non-critical. | Choose MAX6898TTA+T only if fixed long delay suffices and 4 µA higher IQ is acceptable; TPS3898PDRYR provides superior accuracy, flexibility, and efficiency. |
Compared with TPS3898ADRBR and MAX6898TTA+T, the TPS3898PDRYR delivers the tightest threshold accuracy (1%), lowest quiescent current (6 µA), and fastest enable response (0.2 µs), making it optimal for high-reliability, low-power, and timing-critical embedded supervision - especially where board space and thermal budget are constrained.
Availability
TPS3898PDRYR is available at Aetrix Electronics and suitable for FPGA configuration supervision, automotive body control modules, battery-powered real-time clocks, and processor power sequencing requiring stable component supply and guaranteed long-term manufacturability.
Supply support for TPS3898PDRYR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-reliability supervisory circuits for automotive, industrial, and computing markets.
The TPS389x family was engineered specifically for ultra-compact, low-power voltage monitoring in next-generation portable, automotive, and FPGA-based systems - prioritizing precision thresholding, flexible timing, and minimal footprint without sacrificing robustness.
FAQ
What is the function of the CT pin on the TPS3898PDRYR?
The CT pin on the TPS3898PDRYR sets the delay time between SENSE voltage crossing the 500 mV threshold and SENSE_OUT assertion. A capacitor connected from CT to GND determines the delay per tpd(r) = [CCT(µF) × 4] + 40 µs. Leaving CT open yields a fixed 40 µs delay. This pin does not affect ENABLE-to-output timing, which remains 0.2 µs in the P-version. The TPS3898PDRYR uses this for precise power-up sequencing control.
Does the TPS3898PDRYR support monitoring of a 1.2 V supply rail?
Yes, the TPS3898PDRYR supports monitoring of a 1.2 V supply rail using an external resistor divider on the SENSE pin. With its 500 mV base threshold and ±1% accuracy, a 1.2 V rail can be scaled to exactly 500 mV using R1/R2 = 1.4 - for example, R1 = 140 kΩ and R2 = 100 kΩ. The 5 mV hysteresis ensures noise immunity, and the 6 µA quiescent current minimizes loading on the monitored rail. This configuration is explicitly validated in TI's SLVA450 application note for the TPS3898PDRYR.
What is the maximum voltage that can be applied to the SENSE_OUT pin of the TPS3898PDRYR?
The SENSE_OUT pin of the TPS3898PDRYR is rated for up to 18 V when configured as an open-drain output - independent of the VCC supply voltage (1.7 V to 6.5 V). This allows direct interface with higher-voltage logic families or regulators without level shifters. However, a pull-up resistor must be used, and its value must ensure sink current stays within the 1 mA absolute maximum rating - e.g., ≥18 kΩ for 18 V pull-up with ≤1 mA sink. This 18 V rating is specified in Section 7.1 Absolute Maximum Ratings of the TPS3898PDRYR datasheet.
How does the ENABLE pin logic work on the TPS3898PDRYR?
The ENABLE pin on the TPS3898PDRYR is active-low: SENSE_OUT is only allowed to assert low when ENABLE is pulled low *and* SENSE exceeds 500 mV. If ENABLE is high, SENSE_OUT remains high (open-drain, so pulled up externally) regardless of SENSE voltage. When ENABLE transitions from high to low, SENSE_OUT responds within 0.2 µs - a fixed, capacitor-independent delay unique to the P-version. This behavior is defined in Table 2 (TPS3896/8 Truth Table) of the TPS3898PDRYR datasheet.
Is the TPS3898PDRYR suitable for automotive applications?
Yes, the TPS3898PDRYR is qualified for automotive applications with operation across –40°C to 125°C junction temperature and AEC-Q100 stress testing alignment. Its 18 V-tolerant SENSE_OUT supports interface with 12 V automotive subsystems, and its 1% threshold accuracy ensures reliable detection of rail faults under wide temperature and voltage variation. TI documents its use in body control modules and infotainment power domains - confirming suitability for under-hood and cabin environments where the TPS3898PDRYR meets stringent reliability requirements.
TPS3898PDRYR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 6-UFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Simple Reset/Power-On Reset
- Number of Voltages Monitored:
- 1
- Voltage - Threshold:
- Adjustable/Selectable
- Output:
- Open Drain or Open Collector
- Reset:
- Active Low
- Reset Timeout:
- Adjustable/Selectable
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-SON (1.45x1)
TPS3898PDRYR FAQ
1.How can I place an order for TPS3898PDRYR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS3898PDRYR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS3898PDRYR reliable?
The price and inventory of TPS3898PDRYR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS3898PDRYR is usually 5 days.
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Once your TPS3898PDRYR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS3898PDRYR?
For technical support, including TPS3898PDRYR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS3898PDRYR requirements.
6.How does Aetrix verify that TPS3898PDRYR is sourced from the original manufacturer or authorized distributors?
All TPS3898PDRYR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS3898PDRYR meets industry standards.
7.What is the process for return or replacement of TPS3898PDRYR?
All TPS3898PDRYR units undergo pre-shipment inspection (PSI). If there is an issue with TPS3898PDRYR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS3898PDRYR part is unused and in its original packaging.
Return procedure for TPS3898PDRYR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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