Texas Instruments TPS3898PDRYT

Overview

TPS3898PDRYT from Texas Instruments is an ultra-small, single-channel, adjustable voltage supervisor IC with active-low enable and open-drain output. It monitors system supply rails ≥500 mV using an external resistor divider, provides 1% threshold accuracy over –40°C to 125°C, supports capacitor-adjustable delay (40 µs to 190 ms), and draws only 6 µA typical quiescent current. It is used for reliable power-on reset and supply monitoring in space-constrained portable electronics.

For engineers reviewing the TPS3898PDRYT datasheet, TPS3898PDRYT pinout, TPS3898PDRYT application, or TPS3898PDRYT equivalent, key selection criteria include its 0.2-µs enable-to-output propagation delay (P version), 18-V open-drain output rating, 1.7–6.5 V operating range, –40°C to 125°C temperature grade, and USON-6 (1.45 mm × 1.00 mm) package - all critical for low-power, high-density embedded reset design.

Technical Context

The TPS3898PDRYT implements a precision comparator with 5-mV hysteresis and a 0.5-V internal reference, enabling user-defined thresholds down to 500 mV via external resistive dividers. Its active-low ENABLE pin asserts SENSE_OUT low after a fixed 0.2-µs delay when SENSE exceeds V_IT+, bypassing capacitor-based timing for fast enable control.

It features a dedicated CT pin driven by a 310-nA precision current source to charge an external capacitor for adjustable delay timing (tpd(r) = [C_CT × 4] + 40 µs), while maintaining 1% threshold accuracy across temperature and supporting 18-V pull-up independent of V_CC.

Key Specifications

Pinout & Package

TPS3898PDRYT is housed in a 6-pin USON package (1.45 mm × 1.00 mm, 0.5-mm pitch) with wettable flanks for automated optical inspection. The package is moisture-sensitive level 1 (MSL-1) and RoHS-compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar voltage supervisor applications.

Compared with TPS3898ADRBT and MAX6898TTA+T, the TPS3898PDRYT uniquely delivers both ultra-low latency (0.2 µs) and ultra-low power (6 µA), making it optimal for battery-critical, fast-sequencing applications where timing determinism and energy efficiency are jointly constrained.

Availability

TPS3898PDRYT is available at Aetrix Electronics and suitable for portable medical devices, FPGA power management, battery-powered sensor nodes, and automotive infotainment systems requiring stable component supply with guaranteed long-term availability.

Supply support for TPS3898PDRYT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of experience in high-reliability supervisory circuits.

The TPS389x product line was designed specifically for space-constrained, low-power systems requiring precise, configurable voltage monitoring and fast, deterministic reset signaling - targeting portable, industrial, and automotive applications.

FAQ

What is the function of the CT pin on the TPS3898PDRYT?

The CT pin on the TPS3898PDRYT connects to an external capacitor to set the delay time between SENSE rising above V_IT+ and SENSE_OUT assertion. For the P version, this capacitor does not affect ENABLE-to-SENSE_OUT timing (fixed at 0.2 µs), but it determines the delay for SENSE-triggered assertions. With CT open, the default delay is 40 µs; adding a 0.047-µF capacitor yields ~190 ms. The TPS3898PDRYT uses a 310-nA internal current source to charge the capacitor to 1.24 V.

Does the TPS3898PDRYT support monitoring voltages below 1 V?

Yes, the TPS3898PDRYT supports monitoring voltages as low as 500 mV via its internal 0.5-V reference and external resistor divider on the SENSE pin. For example, to monitor a 0.9-V rail, use R1/R2 = 0.8 to set VTARGET = (1 + 0.8) × 0.5 V = 0.9 V. The device maintains 1% threshold accuracy from –40°C to 125°C, and its 5-mV hysteresis ensures clean transitions even with noisy low-voltage rails.

Can the TPS3898PDRYT output drive a 12-V logic input directly?

Yes, the TPS3898PDRYT's open-drain SENSE_OUT is rated to 18 V, allowing direct connection to 12-V logic inputs when pulled up to 12 V via an external resistor. Unlike push-pull outputs, this configuration isolates the 12-V domain from the TPS3898PDRYT's V_CC (1.7–6.5 V), eliminating level-shifter requirements. Ensure the pullup resistor limits sink current to ≤1 mA (e.g., ≥12 kΩ for 12-V pullup) per Electrical Characteristics.

What is the minimum pulse width the ENABLE pin accepts on the TPS3898PDRYT?

The TPS3898PDRYT requires a minimum ENABLE pin pulse width of 1 µs to reliably trigger state changes, as specified in the Timing Requirements table. Its ENABLE input also provides 100-ns glitch rejection, preventing false triggering from noise. Because the TPS3898PDRYT uses an active-low ENABLE, pulling it high for ≥1 µs asserts SENSE_OUT low after the fixed 0.2-µs propagation delay - critical for synchronized power-domain control in multi-IC systems.

How does the TPS3898PDRYT behave during power-up when VCC is ramping?

During V_CC ramp-up, the TPS3898PDRYT remains in reset (SENSE_OUT high-impedance) until V_CC exceeds 1.7 V and stabilizes for ≥50 µs. Below 1.3 V, UVLO disables internal circuitry; between 1.3 V and 1.7 V, output behavior is undefined. Once V_CC ≥1.7 V, the device monitors SENSE and ENABLE. If SENSE > V_IT+ and ENABLE is asserted (low), SENSE_OUT pulls low after 0.2 µs - ensuring clean, monotonic power-on sequencing without spurious resets.