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Texas Instruments TPS5110PW
- Part No.:
- TPS5110PW
- Manufacturer:
- Texas Instruments
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 24-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
TPS5110PW.pdf
- Description:
- IC REG DL BUCK/LNR SYNC 24TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:2,158
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Product details
Overview
TPS5110PW from Texas Instruments is a dual-output synchronous buck controller with integrated LDO controller, designed for low-voltage/high-current I/O power in notebook PCs and DSP systems. It delivers 0.9–3.5 V from the PWM-controlled buck stage (4.5–28 V input) and 0.9–2.5 V from the external-NMOS LDO stage (1.1–3.6 V input), featuring ±1% reference voltage accuracy, 300–500 kHz programmable switching frequency, and temperature-compensated overcurrent protection.
For engineers reviewing the TPS5110PW datasheet, TPS5110PW pinout, TPS5110PW application, or TPS5110PW equivalent, this device supports fast transient response in portable computing power rails, enables skip-mode efficiency optimization under light load, integrates dual independent standby control (STBY/STBY_LDO), and provides coordinated OVP/UVP/FLT latching across both regulators - critical for reliable multi-rail sequencing and fault containment.
Technical Context
The TPS5110PW implements two independent regulation loops: a high-speed PWM/SKIP-mode synchronous buck controller (SBRC) with 2.5 MHz error amplifier bandwidth and an LDO controller driving an external N-channel MOSFET via LDO_GATE with 1.5 mA sink/source capability. Both loops share a precision 0.85 V internal reference and monitor output voltage via INV and INV_LDO pins against ±7% power-good thresholds.
Current protection is resistor-less: SBRC uses temperature-compensated RDS(on) sensing via VIN_SENSE/TRIP with 13 µA nominal trip current, while the LDO employs a 50 mV current-limit threshold on LDO_CUR. Fault handling is unified through a single FLT pin with dual-source current (125 µA for OVP, 2.3 µA for UVP) enabling differentiated latch timing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range (SBRC) | 4.5 V to 28 V - supports wide-input notebook adapter and battery-derived rails without pre-regulation. |
| Input Voltage Range (LDO) | 1.1 V to 3.6 V - enables direct use of buck output or auxiliary supplies as LDO input for ultra-low dropout operation. |
| Reference Voltage | 0.85 V ±1% at 25°C - sets output voltage accuracy and protection thresholds; enables 0.9 V minimum output with tight tolerance. |
| Switching Frequency | 300 kHz to 500 kHz - programmable via CT capacitor; balances EMI, efficiency, and component size for portable designs. |
| Output Drive Capability | OUT_u: ±1.2 A; OUT_d: ±1.5 A - drives low-RDS(on) N-MOSFETs directly; supports high-current phases without gate drivers. |
| Standby Current | <10 µA (typ.) - achieved by grounding STBY/STBY_LDO; enables deep power-down for system-level energy management. |
| Overshoot Protection | LDO_OUT active charge-sink - prevents voltage hump during fast load-decrease transients in I/O rail applications. |
Pinout & Package
PW package: 24-pin plastic TSSOP (0.65 mm pitch), thermally enhanced with exposed pad (JEDEC MO-153), rated for −40°C to +85°C ambient operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| INV | Inverting input (SBRC) | Feedback node for buck regulator; connects to resistor divider from VO1 to set output voltage and enable OVP/UVP detection. |
| INV_LDO | Inverting input (LDO) | Feedback node for LDO regulator; connects to resistor divider from VO2 to set output and trigger LDO-specific protections. |
| LDO_GATE | LDO gate driver output | Drives gate of external N-MOSFET; 1.5 mA sink/−1.4 mA source capability ensures fast turn-on/off for low-dropout operation. |
| OUT_u / OUT_d | High-side / low-side gate drivers | Direct-drive outputs for synchronous buck FETs; OUT_u includes bootstrap (LH/LL) interface; OUT_d referenced to OUTGND. |
| FLT | Fault timer capacitor node | External capacitor sets OVP/UVP latch delay; dual-source current (125 µA/2.3 µA) enables asymmetric fault response timing. |
| POWERGOOD | Open-drain status output | Asserts high only when both SBRC and LDO outputs are within ±7% of target and REG5V_IN > 4 V; supports system sequencing. |
Key Features
| Feature | Design Value |
|---|---|
| Auto PWM/SKIP mode selection | PWM_SEL pin configures dynamic mode switching - maintains >85% efficiency at 10% load without external control logic. |
| Temperature-compensated OCP | ITRIP = 13 µA ±15% with 3400 ppm/°C coefficient - matches MOSFET RDS(on) drift, eliminating calibration resistors and improving overcurrent consistency across temperature. |
| Dual independent standby | STBY and STBY_LDO pins allow selective shutdown of buck or LDO regulator - enables flexible power-state partitioning in multi-rail systems. |
| Integrated overshoot protection | LDO_OUT pin actively sinks charge during fast load release - suppresses >100 mV overshoot spikes without external components. |
| Unified fault latching | Single FLT pin coordinates shutdown of both regulators using shared capacitor - ensures simultaneous fault containment and simplifies board-level fault reporting. |
Applications
| Notebook PC I/O Power | DSP Core/I/O Partitioning |
|---|---|
Use Scenario: Dual-rail power for CPU I/O and chipset interfaces in thin-and-light notebooks with dynamic load profiles. IC Role / Device Role / Timing Role: Primary buck controller (VO1) supplies 1.8 V @ 6 A to memory/bus interfaces; LDO controller (VO2) supplies 1.5 V @ 3 A to low-noise analog peripherals. Use Value: SKIP mode extends battery life during idle; coordinated POWERGOOD enables safe boot sequence; LDO's fast transient response prevents digital glitches during burst data transfers. |
Use Scenario: Independent voltage domains for DSP core logic (1.2 V) and high-speed serial I/O (1.8 V) in real-time signal processing systems. IC Role / Device Role / Timing Role: SBRC powers core domain with programmable soft-start; LDO powers I/O with separate STBY_LDO control for selective interface shutdown. Use Value: Dual standby pins allow I/O retention while core sleeps; LDO's 600 µs fixed soft-start avoids timing conflicts with core rail ramp-up. |
| Consumer Game System Power | Embedded Peripheral Interface Supply |
Use Scenario: Compact, high-efficiency power for handheld gaming devices requiring rapid wake-from-sleep transitions and thermal headroom. IC Role / Device Role / Timing Role: Buck stage powers GPU/memory subsystem; LDO stage powers audio codec and touch controller with ultra-low noise. Use Value: Overshoot protection prevents audio pop during game launch; temperature-compensated OCP maintains reliability under sustained GPU load and case heating. |
Use Scenario: Dedicated low-noise supply for USB PHY, PCIe retimer, or MIPI D-PHY in industrial edge controllers. IC Role / Device Role / Timing Role: LDO controller supplies 1.2 V or 1.5 V rail with <10 µs transient recovery; SBRC provides clean 3.3 V auxiliary rail. Use Value: LDO's 1.4 MHz unity-gain bandwidth ensures sub-µs response to interface protocol bursts; shared FLT pin simplifies fault isolation in multi-interface designs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS51200DRCR | Single-channel 3-A sink/source LDO controller only; no integrated buck controller; supports DDR termination tracking. | Replaces only the LDO function of TPS5110PW; requires external buck IC for VO1 rail. | Select when DDR memory interface support or higher LDO current (3 A) is required, and buck regulation is handled separately. |
| TPS51216RUKR | Dual-output buck controller (no LDO); integrates 5-V LDO for bias; supports Intel VR12.5/VR12.6 protocols. | Targets CPU core voltage regulation with dynamic VID; lacks external-NMOS LDO flexibility and independent LDO feedback. | Select for Intel-compatible CPU power delivery where precise VID sequencing and 5-V bias generation are mandatory. |
Compared with TPS5110PW, TPS51200DRCR offers higher LDO drive but no buck stage, making it suitable only as a partial replacement; TPS51216RUKR provides advanced CPU-specific features but cannot replicate the TPS5110PW's independent LDO control and ultra-low-dropout capability for peripheral rails.
Availability
TPS5110PW is available at Aetrix Electronics and suitable for notebook PC power design, DSP platform development, and consumer electronics embedded power systems requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for TPS5110PW includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in power management ICs for portable and high-performance computing.
The TPS5110PW belongs to TI's notebook power controller product line, engineered specifically to consolidate I/O and peripheral power regulation into a single IC while delivering high efficiency, fast transient response, and robust fault management for space-constrained mobile platforms.
FAQ
What is the maximum output current supported by the TPS5110PW's LDO controller?
The TPS5110PW does not define a fixed maximum LDO output current - it depends on the external N-channel MOSFET selected and thermal design. The LDO_GATE driver provides ±1.5 mA (sink/source), enabling fast switching of MOSFETs with gate charges up to ~20 nC. In the reference EVM, the LDO stage delivers 3 A at 1.5 V, limited by MOSFET RDS(on), PCB layout, and heatsinking - not by the TPS5110PW itself.
How does the TPS5110PW implement temperature compensation for overcurrent protection?
The TPS5110PW integrates a temperature-coefficient circuit that scales the internal trip current source (ITRIP) at 3400 ppm/°C. This matches the positive temperature coefficient of typical N-channel MOSFETs' RDS(on), ensuring consistent current-limit threshold across −40°C to +85°C. The compensation occurs automatically - no external components or calibration are needed.
Can the TPS5110PW operate with only the LDO controller enabled while the buck controller is disabled?
Yes. The TPS5110PW supports independent control: grounding STBY disables only the SBRC (buck controller), while STBY_LDO remains functional. In this state, the LDO controller continues regulating its output, POWERGOOD reflects only LDO status, and LDO_GATE remains active. This allows flexible power-state management - for example, keeping peripheral rails alive while suspending main processor power.
What is the purpose of the LDO_OUT pin beyond being a feedback node?
The LDO_OUT pin serves a dual role: it is both the feedback input for the LDO error amplifier and the active terminal for overshoot protection. When fast load decrease causes output voltage rise, the TPS5110PW sinks current from LDO_OUT to discharge the output capacitor - preventing voltage humps exceeding 100 mV. This eliminates need for external active clamps or larger output capacitance.
Does the TPS5110PW require external compensation components for stability?
Yes - the SBRC loop requires external RC compensation between FB and INV pins to set phase margin and transient response. The LDO loop is internally compensated and needs no external network. For the buck stage, TI's EVM uses R01A/R01B (10 kΩ each) and R03 (18 kΩ) as part of the feedback divider and compensation network; values must be adjusted based on output capacitor ESR and desired bandwidth.
TPS5110PW Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 24-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Bulk
- Product Status:
- Active
- Topology:
- Step-Down (Buck) Synchronous (1), Linear (LDO) (1)
- Number of Outputs:
- 2
- Frequency - Switching:
- 300kHz
- Voltage/Current - Output 1:
- Controller
- Voltage/Current - Output 2:
- Controller
- Voltage/Current - Output 3:
- -
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- No
- Voltage - Supply:
- 1.1V ~ 28V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-TSSOP
TPS5110PW FAQ
1.How can I place an order for TPS5110PW through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS5110PW on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS5110PW reliable?
The price and inventory of TPS5110PW are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS5110PW is usually 5 days.
3.What payment methods are accepted for TPS5110PW?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS5110PW transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS5110PW?
TPS5110PW orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS5110PW order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS5110PW?
For technical support, including TPS5110PW datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS5110PW requirements.
6.How does Aetrix verify that TPS5110PW is sourced from the original manufacturer or authorized distributors?
All TPS5110PW products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS5110PW meets industry standards.
7.What is the process for return or replacement of TPS5110PW?
All TPS5110PW units undergo pre-shipment inspection (PSI). If there is an issue with TPS5110PW, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS5110PW part is unused and in its original packaging.
Return procedure for TPS5110PW:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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