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Texas Instruments TPS51116MPWPEP
- Part No.:
- TPS51116MPWPEP
- Manufacturer:
- Texas Instruments
- Category:
- Special Purpose Regulators
- Package:
- 20-PowerTSSOP (0.173", 4.40mm Width)
- Datasheet:
-
TPS51116MPWPEP.pdf
- Description:
- IC REG CTRLR DDR 1OUT 20HTSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:4,185
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Product details
Overview
TPS51116MPWPEP from Texas Instruments is a radiation-tolerant, extended-temperature synchronous buck controller with integrated 1-A sink/source LDO and buffered VREF for DDR/DDR2/DDR3/LPDDR3 memory power. It delivers 2.5-V (DDR), 1.8-V (DDR2), or adjustable 0.75–3.0-V VDDQ output; ±20-mV VTT/VTTREF accuracy; and supports D-CAP™ mode with 100-ns load-step response in military-grade HTSSOP-20 PowerPAD™ packaging.
For engineers reviewing the TPS51116MPWPEP datasheet, TPS51116MPWPEP pinout, TPS51116MPWPEP application, or TPS51116MPWPEP equivalent, key selection criteria include its dual-mode PWM control (D-CAP™/current mode), RDS(on) or resistor-based current sensing, S3/S4/S5 sleep-state support (including soft-off discharge), and operation across –55°C to 125°C junction temperature.
Technical Context
The TPS51116MPWPEP integrates three tightly coupled power rails: a 400-kHz adaptive on-time synchronous buck controller for VDDQ, a 1-A bidirectional LDO for VTT, and a buffered 10-mA VTTREF output tracking VDDQ/2. Its D-CAP™ mode enables zero-external-compensation operation with ceramic capacitors, while current mode supports ultra-low-ESR stability via external COMP network.
Control logic implements JEDEC-compliant DDR memory power sequencing: high-Z VTT in S3 (suspend-to-RAM); simultaneous VDDQ/VTT/VTTREF discharge in S4/S5 (soft-off); and independent VLDOIN input to minimize LDO conduction loss. Protection includes overvoltage (±5% VDDQ OVP), undervoltage (70% UVP), thermal shutdown (160°C), and cycle-by-cycle current limiting with RDS(on) temperature compensation (4500 ppm/°C).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDDQ Output Range | 2.5 V (DDR), 1.8 V (DDR2), or 0.75–3.0 V adjustable - matches JEDEC SSTL/HSTL termination standards |
| VTT Output Capability | ±1 A sink/source - enables active termination for DDRx/LPDDR3 bidirectional data lines |
| VTTREF Accuracy | ±20 mV at no load, ±40 mV at full load - ensures precise VDDQ/2 tracking for SSTL-2/18/15 reference compliance |
| Load Step Response | 100 ns in D-CAP™ mode - maintains VDDQ regulation during DDR burst-mode transitions |
| Operating Temperature | –55°C to 125°C junction - qualified for defense, aerospace, and medical embedded systems |
| Switching Frequency | Fixed 400 kHz pseudo-constant frequency with adaptive on-time - balances efficiency and EMI in space-constrained designs |
| Current Sensing | RDS(on) or external resistor - eliminates sense resistor loss or enables precision current limit calibration |
Pinout & Package
TPS51116MPWPEP is housed in a thermally enhanced 20-pin HTSSOP PowerPAD™ (PWP) package with exposed thermal pad for PCB heat sinking. Pin count, layout, and thermal metrics (θJCbot = 3.6°C/W) are optimized for high-power density DDR memory power delivery.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VLDOIN (1) | LDO input supply | External connection point to reduce LDO power loss by sourcing from lower-voltage rail instead of VDDQ |
| VTT (2) | VTT LDO output | 1-A bidirectional output driving DDR termination; requires remote VTTSNS sensing for ±20-mV accuracy |
| VTTGND (3) | VTT LDO ground return | Dedicated low-impedance ground path for VTT loop stability and noise isolation |
| VTTSNS (4) | VTT voltage sense input | Remote sensing node connected to VTT capacitor anode - enables Kelvin sensing to reject PCB trace IR drop |
| GND (5) | Signal ground reference | Reference for internal circuits and VTT capacitor negative terminal |
| MODE (6) | Discharge mode select | Configures VDDQ/VTT discharge behavior: tracking (via LDO transistors) or non-tracking (via internal FETs) |
| VTTREF (7) | Buffered reference output | Low-noise 10-mA VDDQ/2 reference for SSTL/HSTL termination; ±20-mV tolerance ensures JEDEC compliance |
| COMP (8) | Compensation network interface | Selects control mode: tied to V5IN → D-CAP™; otherwise → current mode with external RC network |
| VDDQSNS (9) | VDDQ feedback and VTTREF source | Senses VDDQ output; generates VTTREF internally; also serves as non-tracking discharge path |
| VDDQSET (10) | VDDQ voltage setting | Selects preset (GND=2.5 V, V5IN=1.8 V) or adjustable output via external resistor divider |
| S3 (11) | Suspend-to-RAM input | Asserts high-Z state on VTT during S3 - eliminates standby leakage in DDR memory subsystems |
| S5 (12) | Suspend-to-disk input | Triggers soft-off discharge of VDDQ/VTT/VTTREF in S4/S5 states per JEDEC specification |
| PGOOD (13) | Power-good open-drain output | Signals VDDQ in regulation (95–105% window); drives system enable logic or FPGA configuration sequencer |
| V5IN (14) | 5-V bias supply | Powers internal logic, gate drivers, and COMP amplifier; requires local 10-μF ceramic decoupling |
| CS (15) | Current sense input | Accepts RDS(on) voltage (LL–PGND) or resistor drop (sense resistor–PGND) for cycle-by-cycle overcurrent protection |
| PGND (16) | Power ground return | Common return for VTT LDO, PGOOD comparator, and current sense circuitry - critical for noise immunity |
| DRVL (17) | Bottom MOSFET gate driver | Drives N-channel sync rectifier; 0.9 Ω sink resistance minimizes conduction loss during light-load DCM |
| LL (18) | Low-side switch node | Connects to drain of bottom MOSFET; used for RDS(on) sensing and VIN feed-forward in adaptive on-time control |
| DRVH (19) | Top MOSFET gate driver | Bootstrap-driven N-channel gate driver; 3 Ω source resistance supports fast turn-on of high-Qg MOSFETs |
| VBST (20) | Bootstrap capacitor input | Supplies floating gate drive voltage for DRVH; requires 0.1-μF ceramic capacitor between VBST and LL |
Key Features
| Feature | Design Value |
|---|---|
| D-CAP™ adaptive on-time control | Enables stable 20-μF ceramic-only VDDQ output without external compensation components |
| Bidirectional 1-A VTT LDO | Maintains ±20-mV VTT regulation during DDR read/write transitions without requiring large bulk capacitance |
| JEDEC-compliant S3/S4/S5 control | Automatically places VTT in high-Z (S3) or discharges VDDQ/VTT/VTTREF (S4/S5) - eliminates need for external sequencing IC |
| Temperature-compensated RDS(on) sensing | 4500 ppm/°C ITRIP slope matches MOSFET RDS(on) drift - ensures consistent overcurrent protection across –55°C to 125°C |
| Buffered VTTREF with ±20-mV accuracy | Provides low-noise, high-current VDDQ/2 reference directly compliant with SSTL-2/18/15 and HSTL specifications |
| Thermally enhanced HTSSOP PowerPAD™ | θJCbot = 3.6°C/W enables >3 W dissipation in compact footprint - suitable for high-density memory modules |
Applications
| DDR Memory Power Supply | DDR2 Memory Power Supply |
|---|---|
Use Scenario: Powering DDR SDRAM in avionics flight control computers requiring radiation-hardened, wide-temperature operation. IC Role / Device Role / Timing Role: Delivers regulated 2.5-V VDDQ, ±1-A VTT, and buffered VTTREF for SSTL-2 termination with 100-ns transient response. Use Value: Eliminates external sequencing and discrete LDOs, reducing BOM count by 4+ components while meeting DO-254 DAL-A timing integrity requirements. |
Use Scenario: Supplying DDR2 SDRAM in satellite payload processors operating at –55°C to 125°C ambient. IC Role / Device Role / Timing Role: Generates 1.8-V VDDQ and VTT with ±20-mV VTTREF tracking for SSTL-18 compliance under extreme thermal cycling. Use Value: Achieves <1.5% total output error across temperature via integrated RDS(on) current sensing and VLDOIN optimization - avoids derating penalties. |
| DDR3/LPDDR3 Adjustable Output | Military Radar Memory Subsystem |
Use Scenario: Configurable memory power for field-upgradable COTS radar modules supporting DDR3 (1.5 V) and LPDDR3 (1.2 V) interfaces. IC Role / Device Role / Timing Role: Uses VDDQSET resistor divider to set VDDQ from 0.75 V to 3.0 V; VTTREF automatically tracks VDDQ/2. Use Value: Single SKU supports multiple memory generations - reduces inventory complexity and enables hardware reuse across platform variants. |
Use Scenario: High-reliability DDR3 memory power in ground-based radar signal processors deployed in desert environments. IC Role / Device Role / Timing Role: Provides VDDQ, VTT, and VTTREF with soft-off discharge (S4/S5) and thermal shutdown (160°C) for mission-critical fault containment. Use Value: Meets MIL-STD-810H thermal shock and MIL-STD-704E power interruption requirements without external supervision circuitry. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar DDR memory power management applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS51200DRCR | Single-channel DDR3/LPDDR3 VTT regulator only; no VDDQ controller or VTTREF buffer | Requires external VDDQ buck controller and reference; suited for designs where VDDQ is already generated | Choose when only VTT regulation is needed and system-level VDDQ is available from another source |
| ISL95812IRZ-T | Supports DDR4; higher VDDQ max (1.35 V); lacks S3/S4/S5 sleep-state logic and RDS(on) sensing | Designed for newer DDR4 memory; does not meet JEDEC S3/S4/S5 discharge requirements for legacy DDR/DDR2 | Prefer for DDR4 systems; avoid for DDR/DDR2/DDR3 where soft-off and high-Z control are mandatory |
Compared with TPS51200DRCR and ISL95812IRZ-T, the TPS51116MPWPEP uniquely integrates VDDQ buck control, VTT LDO, and VTTREF in one military-qualified package with full JEDEC sleep-state compliance - making it the only single-chip solution for radiation-tolerant DDR/DDR2/DDR3 memory power.
Availability
TPS51116MPWPEP is available at Aetrix Electronics and suitable for defense electronics, aerospace avionics, and medical imaging systems requiring stable component supply across extended temperature and long product lifecycles.
Supply support for TPS51116MPWPEP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-reliability ICs for industrial, automotive, and aerospace markets.
The TPS51116MPWPEP belongs to TI's Enhanced Product (EP) line - engineered for defense, aerospace, and medical applications with controlled baseline, extended temperature range (–55°C to 125°C), and full traceability.
FAQ
What is the maximum supported VDDQ output voltage for TPS51116MPWPEP?
The TPS51116MPWPEP supports an adjustable VDDQ output range from 0.75 V to 3.0 V. It also provides fixed 2.5-V (DDR) and 1.8-V (DDR2) outputs via VDDQSET pin configuration. The upper limit of 3.0 V accommodates future DDR standards and custom memory interfaces requiring higher termination voltages, all while maintaining ±20-mV VTTREF accuracy relative to VDDQ/2.
Does TPS51116MPWPEP support both RDS(on) and resistor-based current sensing?
Yes, the TPS51116MPWPEP supports dual current sensing schemes. For RDS(on) sensing, connect CS to V5IN through a trip-setting resistor and tie LL to the bottom MOSFET drain. For resistor sensing, connect CS directly to the sense resistor–PGND node. The device uses 4500 ppm/°C temperature compensation on ITRIP current to match MOSFET RDS(on) drift - a feature confirmed in the Electrical Characteristics table under TCITRIP.
How does TPS51116MPWPEP handle DDR memory sleep states S3, S4, and S5?
The TPS51116MPWPEP implements JEDEC-compliant sleep-state control: S3 asserts high-Z on VTT; S4/S5 trigger soft-off discharge of VDDQ, VTT, and VTTREF. MODE pin selects tracking (discharge via LDO transistors) or non-tracking (discharge via internal FETs) behavior. These functions are fully integrated - no external logic or sequencing ICs are required to meet DDR/DDR2/DDR3 specification requirements.
What is the purpose of the VLDOIN pin on TPS51116MPWPEP?
The VLDOIN pin on TPS5116MPWPEP provides an independent input supply for the VTT LDO, enabling designers to connect it to a lower-voltage rail (e.g., 1.5 V or 1.2 V) instead of VDDQ. This reduces conduction loss during VTT sourcing, improving overall system efficiency - especially critical in high-current DDR3/LPDDR3 applications where VTT can draw up to 1 A continuously.
Can TPS51116MPWPEP operate without external compensation components?
Yes, the TPS51116MPWPEP supports D-CAP™ mode, which disables the transconductance amplifier and uses internal compensation. When COMP is tied to V5IN, the device operates in D-CAP™ mode and requires only a 20-μF ceramic output capacitor on VDDQ - eliminating external RC networks, simplifying layout, and reducing BOM cost while maintaining stability and 100-ns transient response.
TPS51116MPWPEP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 20-PowerTSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Applications:
- Controller, DDR
- Voltage - Input:
- 3V ~ 28V
- Number of Outputs:
- 1
- Voltage - Output:
- 1.2V, 1.5V, 1.8V, 2.5V, Adj
- Operating Temperature:
- -55°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-HTSSOP
TPS51116MPWPEP FAQ
1.How can I place an order for TPS51116MPWPEP through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS51116MPWPEP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS51116MPWPEP reliable?
The price and inventory of TPS51116MPWPEP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS51116MPWPEP is usually 5 days.
3.What payment methods are accepted for TPS51116MPWPEP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS51116MPWPEP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS51116MPWPEP?
TPS51116MPWPEP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS51116MPWPEP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS51116MPWPEP?
For technical support, including TPS51116MPWPEP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS51116MPWPEP requirements.
6.How does Aetrix verify that TPS51116MPWPEP is sourced from the original manufacturer or authorized distributors?
All TPS51116MPWPEP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS51116MPWPEP meets industry standards.
7.What is the process for return or replacement of TPS51116MPWPEP?
All TPS51116MPWPEP units undergo pre-shipment inspection (PSI). If there is an issue with TPS51116MPWPEP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS51116MPWPEP part is unused and in its original packaging.
Return procedure for TPS51116MPWPEP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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