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Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Special Purpose Regulators

Texas Instruments TPS51116RGE

Name: TPS51116RGE
Brand: Texas Instruments
SKU: TPS51116RGE
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: TPS51116RGE

Manufacturer:: Texas Instruments

Category:: Special Purpose Regulators

Package:: 24-VFQFN Exposed Pad

Datasheet:: TPS51116RGE.pdf

Description:: IC REG CTRLR DDR 1OUT 24VQFN

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Product details

Overview

TPS51116RGE from Texas Instruments is a complete DDR/DDR2/DDR3/DDR3L/LPDDR3/DDR4 memory power solution integrating a synchronous buck controller (VDDQ), 3-A sink/source LDO (VTT), and buffered 10-mA reference (VREF). It delivers 2.5-V (DDR), 1.8-V (DDR2), or adjustable 0.75–3.0-V VDDQ output with ±20-mV accuracy on both VTT and VREF, supporting SSTL-2, SSTL-18, SSTL-15, and HSTL termination in high-density memory subsystems.

For engineers reviewing the TPS51116RGE datasheet, TPS51116RGE pinout, TPS51116RGE application, or TPS51116RGE equivalent, key selection criteria include D-CAP™ vs current-mode operation support, S3/S4/S5 sleep-state control for VDDQ/VTT discharge, thermal shutdown, and compatibility with ceramic output capacitors requiring only 20 µF total for the VTT LDO.

Technical Context

The TPS51116RGE implements adaptive on-time D-CAP™ control for sub-100-ns load-step response and supports current-mode operation for enhanced stability with ceramic output capacitors. Its dual-path architecture separates VDDQ regulation (400-kHz pseudo-constant-frequency PWM) from VTT tracking (sourced from VDDQSNS), enabling independent voltage setpoints and fast transient recovery.

VTT regulation operates as a sink/source LDO with external VLDOIN input to minimize power loss, while VTTREF provides a low-noise, buffered half-VDDQSNS reference with ±20-mV tolerance across temperature and load. Sleep-state logic (S3/S5 pins) controls high-Z mode and soft-off discharge sequences without external circuitry.

Key Specifications

Parameter	Value and Actual Design Meaning
VDDQ Output Range	0.75–3.0 V; supports DDR (2.5 V), DDR2 (1.8 V), DDR3 (1.5 V), DDR3L (1.35 V), LPDDR3/DDR4 (1.2 V) with ±20 mV tolerance at full load.
VTT Output Capability	±3 A sink/source; tracks VTTREF (VDDQSNS/2) with ±40 mV tolerance at \|I_VTT\| ≤ 3 A, enabling bidirectional termination for DDR buses.
Switching Frequency	Fixed ~400 kHz; adaptive on-time D-CAP™ mode enables 100-ns load-step response; current-mode option allows ceramic capacitor optimization.
VTTREF Accuracy	±20 mV over temperature and load; buffered 10-mA output referenced to VDDQSNS, used for VTT regulation and SSTL/HSTL biasing.
Thermal Protection	Thermal shutdown at 160°C with 10°C hysteresis; R_θJA = 35.3°C/W (RGE QFN) ensures reliable operation up to 85°C ambient.
Sleep-State Control	S3 input places VTT in high-Z during suspend-to-RAM; S5 triggers soft-off discharge of VDDQ, VTT, and VTTREF in suspend-to-disk states.
Package	24-pin QFN (4 mm × 4 mm, 0.5-mm pitch); PowerPAD™ thermal pad improves heat dissipation and PCB layout flexibility.

Pinout & Package

TPS51116RGE uses a 24-pin QFN package (4 mm × 4 mm, 0.5-mm pitch) with exposed thermal pad (PowerPAD™) for enhanced thermal performance. Pin numbering follows top-view orientation per TI SLUS609J Rev J.

Pin	Circuit Role	Design Meaning
1	VTTGND	Power ground return for VTT LDO output; must connect directly to VTT capacitor negative terminal.
2	VTTSNS	VTT output voltage sense input; connects to positive terminal of VTT output capacitor for accurate regulation.
3	GND	Signal ground reference for internal comparators and control circuits; separate from PGND and VTTGND.
4	MODE	Discharge mode select: high = non-tracking VDDQ discharge; low = tracking discharge with VTT/VTTREF.
5	VTTREF	Buffered reference output (VDDQSNS/2); supplies low-noise bias for SSTL/HSTL termination and VTT feedback.
6	COMP	Transconductance amplifier output; connects to V5FILT for D-CAP™ mode or external compensation network for current mode.
7	VDDQSNS	VDDQ reference input for VTT/VTTREF generation; also serves as VDDQ feedback when VDDQSET is tied to GND/V5IN.
8	VDDQSET	VDDQ output voltage programming pin; sets 2.5 V (0 V), 1.8 V (5 V), or adjustable mode via resistor divider.
9	S3	Suspend-to-RAM control input; asserts high-Z state on VTT output when pulled low.
10	S5	Suspend-to-disk control input; initiates soft-off discharge of VDDQ, VTT, and VTTREF when pulled low.
11	NC	No-connect pin; must remain unconnected per datasheet.
12	PGOOD	Open-drain power-good indicator; goes high when VDDQ is within ±5% of target; drives external enable logic.
13	PGND	Power ground for low-side MOSFET gate driver and current-sense comparator; ties to source of DRVL.
14	V5FILT	Filtered 5-V supply input for internal circuits; requires RC filter from V5IN to reduce noise on control loop.
15	V5IN	Main 4.75–5.25-V supply for internal logic and gate drivers; powers V5FILT via external RC network.
16	CS	Current-sense comparator input (−); sets overcurrent threshold via resistor or interfaces with R_DS(on) sensing.
17	DRVL	Low-side MOSFET gate driver output; drives IRF7832-type N-channel FET with 0.9–3 Ω sink/source resistance.
18	LL	High-side gate driver return and R_DS(on) current-sense (−) input; connects to source of high-side FET.
19	DRVH	High-side MOSFET gate driver output; drives IRF7821-type N-channel FET with 0.9–3 Ω sink/source resistance.
20	VBST	Bootstrap capacitor input for high-side driver; requires external 0.1-µF ceramic capacitor between VBST and LL.
21	CS_GND	Current-sense comparator input (+) and PGOOD ground reference; connects to PGND for accurate sensing.
22	VLDOIN	VTT LDO input supply; connects to VDDQ output to minimize dropout loss or to auxiliary rail for efficiency optimization.
23	VTT	VTT LDO output; delivers ±3 A sink/source current with fast transient response using only 20 µF ceramic capacitance.
24	VDDQ	VDDQ buck regulator output; supplies DDR memory core voltage with overvoltage (115%) and undervoltage (70%) protection.

Key Features

Feature	Design Value
D-CAP™ adaptive on-time control	Enables 100-ns load-step response without external compensation; simplifies design for DDR memory applications with tight transient requirements.
VTT sink/source LDO with VLDOIN input	Reduces power loss by allowing VLDOIN to be sourced from VDDQ or an optimized auxiliary rail-critical for thermal management in compact systems.
Integrated VTTREF buffer	Provides low-noise, ±20-mV-accurate VDDQSNS/2 reference for SSTL/HSTL termination without external op-amps or resistive dividers.
S3/S5 sleep-state logic	Automatically places VTT in high-Z during S3 and discharges VDDQ/VTT/VTTREF in S4/S5-eliminates need for external discharge FETs or sequencing ICs.
24-pin QFN with PowerPAD™	Delivers 35.3°C/W junction-to-ambient thermal resistance and supports high-current routing with exposed thermal pad soldered to PCB ground plane.

Applications

DDR2 Memory Power Supply	SSTL-18 Termination System
Use Scenario: Powering DDR2 SDRAM modules in industrial embedded controllers requiring stable 1.8-V VDDQ and matched 0.9-V VTT. IC Role / Device Role / Timing Role: TPS51116RGE acts as the primary memory power controller-regulating VDDQ via synchronous buck and generating precise VTT/VTTREF from VDDQSNS. Use Value: Achieves ±20-mV VTT accuracy at ±2 A load and supports soft-off discharge during system suspend, reducing standby power by >90% versus discrete solutions.	Use Scenario: Providing termination voltage for SSTL-18 I/O interfaces in FPGA-based communication baseband boards. IC Role / Device Role / Timing Role: TPS51116RGE delivers low-noise, buffered VTTREF and actively sinks/sources current on VTT to maintain signal integrity across 100+ MHz data rates. Use Value: Eliminates external op-amp buffers and discrete discharge FETs; VTT load regulation stays within ±30 mV from –2 A to +2 A, ensuring clean eye diagrams.
DDR4 Memory Subsystem	LPDDR3 Mobile SoC Power
Use Scenario: Powering DDR4 DIMMs in server memory modules where space constraints demand integrated VDDQ/VTT/VTTREF in one package. IC Role / Device Role / Timing Role: TPS51116RGE configures VDDQ to 1.2 V and VTT to 0.6 V using adjustable mode, while VTTREF provides precise half-VDDQSNS reference for on-die termination calibration. Use Value: Reduces BOM count by 7 components versus discrete buck + LDO + reference; maintains ±40-mV VTT tolerance at 1.5-A sink, meeting JEDEC DDR4 spec.	Use Scenario: Supplying LPDDR3 memory rails in portable medical imaging devices needing ultra-low quiescent current and thermal efficiency. IC Role / Device Role / Timing Role: TPS51116RGE operates in S3 high-Z mode during idle periods and leverages VLDOIN connection to VDDQ to minimize dropout loss in battery-sensitive designs. Use Value: Cuts VTT LDO power loss by 45% versus fixed-input LDOs; IV_LDOIN2 = 0.1–10 µA in S3 state extends battery life without compromising wake-up latency.

DDR2 Memory Power Supply

SSTL-18 Termination System

Use Scenario: Powering DDR2 SDRAM modules in industrial embedded controllers requiring stable 1.8-V VDDQ and matched 0.9-V VTT.

IC Role / Device Role / Timing Role: TPS51116RGE acts as the primary memory power controller-regulating VDDQ via synchronous buck and generating precise VTT/VTTREF from VDDQSNS.

Use Value: Achieves ±20-mV VTT accuracy at ±2 A load and supports soft-off discharge during system suspend, reducing standby power by >90% versus discrete solutions.

Use Scenario: Providing termination voltage for SSTL-18 I/O interfaces in FPGA-based communication baseband boards.

IC Role / Device Role / Timing Role: TPS51116RGE delivers low-noise, buffered VTTREF and actively sinks/sources current on VTT to maintain signal integrity across 100+ MHz data rates.

Use Value: Eliminates external op-amp buffers and discrete discharge FETs; VTT load regulation stays within ±30 mV from –2 A to +2 A, ensuring clean eye diagrams.

DDR4 Memory Subsystem

LPDDR3 Mobile SoC Power

Use Scenario: Powering DDR4 DIMMs in server memory modules where space constraints demand integrated VDDQ/VTT/VTTREF in one package.

IC Role / Device Role / Timing Role: TPS51116RGE configures VDDQ to 1.2 V and VTT to 0.6 V using adjustable mode, while VTTREF provides precise half-VDDQSNS reference for on-die termination calibration.

Use Value: Reduces BOM count by 7 components versus discrete buck + LDO + reference; maintains ±40-mV VTT tolerance at 1.5-A sink, meeting JEDEC DDR4 spec.

Use Scenario: Supplying LPDDR3 memory rails in portable medical imaging devices needing ultra-low quiescent current and thermal efficiency.

IC Role / Device Role / Timing Role: TPS51116RGE operates in S3 high-Z mode during idle periods and leverages VLDOIN connection to VDDQ to minimize dropout loss in battery-sensitive designs.

Use Value: Cuts VTT LDO power loss by 45% versus fixed-input LDOs; IV_LDOIN2 = 0.1–10 µA in S3 state extends battery life without compromising wake-up latency.

Equivalent & Alternatives

The following parts are listed as comparable options for similar DDR memory power management applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
TPS51216RGE	Includes integrated MOSFET drivers with higher peak current (±4 A VTT), improved VDDQ efficiency at light load, and extended VIN range (up to 28 V).	Targeted for DDR3/DDR4 systems requiring higher VTT current headroom and tighter light-load regulation.	Select TPS51216RGE when VTT peak current exceeds 3 A or when operating from >12-V input rails; TPS51116RGE remains optimal for cost-sensitive DDR2/DDR3 designs with ≤3-A VTT.
ISL95812IRZ	Offers dual-output synchronous buck (VDDQ + VPP) plus 3-A VTT LDO; lacks buffered VTTREF but adds programmable VDDQ tracking and PMBus interface.	Suitable for DDR3L/DDR4 systems requiring dynamic voltage scaling and telemetry, not just fixed-rail memory power.	Choose ISL95812IRZ for systems needing digital control and VPP generation; TPS51116RGE is preferred for analog-only, low-complexity DDR2–DDR4 termination with guaranteed VTTREF accuracy.

Compared with TPS51216RGE and ISL95812IRZ, the TPS51116RGE delivers the lowest component count for standard DDR2–DDR4 termination with proven ±20-mV VTT/VTTREF accuracy, while avoiding unnecessary complexity like PMBus or dual-buck integration where only single-rail VDDQ and VTT are required.

Availability

TPS51116RGE is available at Aetrix Electronics and suitable for DDR2/DDR3/DDR4 memory power supplies, SSTL/HSTL termination systems, and LPDDR3 mobile SoC designs requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.

Supply support for TPS51116RGE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in memory interface power solutions.

The TPS51116RGE belongs to TI's DDR memory power management product line, designed specifically to integrate VDDQ regulation, VTT termination, and VTTREF buffering into a single IC-reducing board area, BOM cost, and design risk for high-speed memory subsystems.

FAQ

What is the maximum supported DDR standard for the TPS51116RGE?

The TPS51116RGE supports DDR, DDR2, DDR3, DDR3L, LPDDR3, and DDR4 memory standards. It achieves this through configurable VDDQ output (0.75–3.0 V), precise VTT tracking (VDDQSNS/2), and buffered VTTREF-all validated per JEDEC specifications for each standard's voltage and timing requirements.

Does the TPS51116RGE require external compensation components in D-CAP™ mode?

No, the TPS51116RGE does not require external compensation components in D-CAP™ mode. When the COMP pin is connected to V5FILT, the device operates in adaptive on-time D-CAP™ mode, which is inherently stable with ceramic output capacitors and eliminates the need for external RC networks or type-II/type-III compensators.

How does the TPS51116RGE handle VTT discharge during system suspend states?

The TPS51116RGE uses dedicated S3 and S5 pins to manage VTT discharge: pulling S3 low places VTT in high-Z mode for suspend-to-RAM, while pulling S5 low initiates soft-off discharge of VTT (and VDDQ/VTTREF) for suspend-to-disk. Discharge current is internally controlled-no external FETs or resistors are needed.

What is the minimum output capacitance required for the VTT LDO in the TPS51116RGE?

The VTT LDO in the TPS51116RGE requires only 20 µF of total ceramic output capacitance-typically implemented as two 10-µF X5R/X7R capacitors-to ensure stability and meet transient response specs. This is significantly lower than discrete LDO solutions, reducing board area and cost.

Can the TPS51116RGE operate with both D-CAP™ and current-mode control simultaneously?

No, the TPS51116RGE supports either D-CAP™ mode (COMP tied to V5FILT) or current-mode control (COMP connected to external compensation network), but not both simultaneously. The mode is selected at startup and remains fixed; switching modes dynamically is not supported per the datasheet.

TPS51116RGE Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: -

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tube

Product Status:: Obsolete

Applications:: Controller, DDR

Voltage - Input:: 3V ~ 28V

Number of Outputs:: 1

Voltage - Output:: 1.2V, 1.35V, 1.5V, 1.8V, 2.5V, Adj

Operating Temperature:: -40°C ~ 85°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 24-VQFN (4x4)

TPS51116RGE FAQ

1.How can I place an order for TPS51116RGE through Aetrix?

Please submit a Request for Quotation (RFQ) for TPS51116RGE on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for TPS51116RGE reliable?

The price and inventory of TPS51116RGE are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS51116RGE is usually 5 days.

3.What payment methods are accepted for TPS51116RGE?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS51116RGE transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for TPS51116RGE?

TPS51116RGE orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your TPS51116RGE order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for TPS51116RGE?

For technical support, including TPS51116RGE datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS51116RGE requirements.

6.How does Aetrix verify that TPS51116RGE is sourced from the original manufacturer or authorized distributors?

All TPS51116RGE products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS51116RGE meets industry standards.

7.What is the process for return or replacement of TPS51116RGE?

All TPS51116RGE units undergo pre-shipment inspection (PSI). If there is an issue with TPS51116RGE, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The TPS51116RGE part is unused and in its original packaging.

Return procedure for TPS51116RGE:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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