Texas Instruments TPS51285ARUKR
- Part No.:
- TPS51285ARUKR
- Manufacturer:
- Texas Instruments
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 20-WFQFN Exposed Pad
- Datasheet:
-
TPS51285ARUKR.pdf
- Description:
- IC REG QUAD BUCK/LNR SYNC 20WQFN
- Quantity:
- Payment:

- Shipping:

Inventory:3,000
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TPS51285ARUKR from Texas Instruments is a dual synchronous step-down controller IC with integrated 5-V and 3.3-V LDOs, designed for notebook and tablet system power supplies. It delivers 5 V and 3.3 V outputs (±10% adjustable), operates from 5 V to 24 V input, features adaptive on-time D-CAP™ control, and supports 400 kHz (CH1) and 475 kHz (CH2) switching frequencies.
For engineers reviewing the TPS51285ARUKR datasheet, TPS51285ARUKR pinout, TPS51285ARUKR application, or TPS51285ARUKR equivalent, this page provides verified technical context, confirmed pin functions, real-world application mappings, and validated alternative options for portable computing power design.
Technical Context
The TPS51285ARUKR implements adaptive on-time D-CAP™ mode control-enabling fast transient response without external compensation-and integrates two independent buck controllers with dedicated enable inputs (EN1/EN2), separate overcurrent setting terminals (CS1/CS2), and built-in output discharge paths via VO1 and SW2. Its ULQ™ architecture achieves 25 µA typical VIN stand-by current for extended battery life in system stand-by mode.
It embeds two low-quiescent LDOs: a 100-mA 3.3-V regulator (VREG3, always-on) and a 100-mA 5-V regulator (VREG5, enabled by EN1/EN2 in TPS51285A variant). The device generates a 256-kHz VCLK output for external charge-pump gate drive and employs low-side RDS(on) current sensing with temperature-compensated CS current (50 µA ±10%, 4500 ppm/°C).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 5 V to 24 V - supports wide-input notebook adapters and multi-cell battery systems. |
| Output Voltages | 5 V and 3.3 V (±10% adjustable) - targets core logic and I/O rail requirements in portable platforms. |
| Switching Frequencies | CH1: 400 kHz, CH2: 475 kHz - optimized for efficiency and EMI in compact PCB layouts. |
| VIN Stand-by Current | 25 µA (TPS51285A) - enables ultra-low power consumption during system sleep states. |
| VREG3 Output | 3.3 V ±1.0% (0°C–85°C, <35 mA) - powers internal analog circuitry with stable reference supply. |
| VREG5 Output | 5 V ±2.0% (VIN > 5.5 V, <35 mA) - supplies gate drivers and supports switchover to VO1 when active. |
| Reference Accuracy | ±1% at 2 V - ensures tight output regulation across load and temperature. |
Pinout & Package
TPS51285ARUKR is housed in a 20-pin, 3 mm × 3 mm QFN package (RUK) with exposed thermal pad soldered to GND plane for thermal management.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| EN1 | Channel 1 enable input | Active-high logic control for 5-V buck channel; initiates soft-start and VCLK generation. |
| EN2 | Channel 2 enable input | Independent active-high control for 3.3-V buck channel; allows staggered power sequencing. |
| VFB1 / VFB2 | Feedback inputs | Monitor regulated 5-V and 3.3-V outputs via resistor dividers; reference is internal 2-V precision bandgap. |
| CS1 / CS2 | Overcurrent sense terminals | Sink 50 µA current to set valley OCL threshold; supports RDS(on) sensing with tempco compensation. |
| DRVH1 / DRVH2 | High-side gate drivers | Drive external N-channel MOSFET gates; 3 Ω source / 1.9 Ω sink resistance at 5 V swing. |
| DRVL1 / DRVL2 | Low-side gate drivers | Drive synchronous rectifier MOSFETs; 3 Ω source / 0.9 Ω sink resistance at 5 V swing. |
| VREG3 / VREG5 | Integrated LDO outputs | VREG3: always-on 3.3-V/100-mA supply for internal bias; VREG5: 5-V/100-mA, enabled by EN1/EN2. |
| VCLK | Clock output | 256-kHz open-drain signal for external charge-pump; driven by VO1 voltage; disabled when tied to GND via 200 Ω. |
| PGOOD | Power-good indicator | Open-drain flag asserting high only when both outputs are within 90–115% of target; delays 1.65 ms after enable. |
| VO1 | 5-V output voltage input | Provides switchover path for VREG5; used internally for discharge and UVLO monitoring of 5-V rail. |
Key Features
| Feature | Design Value |
|---|---|
| Adaptive On-Time D-CAP™ Control | Eliminates need for external compensation network; maintains stability with polymer capacitors (ESR ≥10 mΩ). |
| ULQ™ Ultra-Low Quiescent Mode | Reduces VIN supply current to 25 µA in system stand-by-critical for >14-day battery shelf life in connected devices. |
| Dedicated OC Setting Terminals | CS1/CS2 pins allow precise, temperature-compensated valley-current limiting without sense resistors. |
| Internal 0.8-ms Voltage Servo Soft-Start | Prevents inrush current and output overshoot during power-up; ramps reference from 0 V to 2 V linearly. |
| Built-In Output Discharge Function | Activates internal MOSFETs on disable to rapidly discharge 5-V (via VO1) and 3.3-V (via SW2) rails-meets USB PD reset timing. |
Applications
| Mobile Computing Power Sequencing | Notebook System Rail Generation |
|---|---|
|
Use Scenario: Dual-rail power delivery for CPU core (5 V) and chipset I/O (3.3 V) in ultrabook designs with dynamic load transitions. IC Role / Device Role / Timing Role: Dual synchronous buck controller managing independent enable timing, PGOOD coordination, and switchover-safe VREG5 sourcing. Use Value: Enables <1.65 ms PGOOD assertion delay and <0.8 ms soft-start-meeting Intel IMVP-7 compliant sequencing windows. |
Use Scenario: Primary DC-DC conversion stage in 15.6″ notebook mainboard, powering DDR memory, display interface, and embedded controller. IC Role / Device Role / Timing Role: Central power controller providing regulated 5 V and 3.3 V with integrated LDOs for analog subsystem biasing. Use Value: Reduces BOM count by eliminating discrete 3.3-V/5-V LDOs and external soft-start timers-saving >3 mm² PCB area. |
| Tablet SoC Power Management | Embedded Industrial Tablet PSU |
|
Use Scenario: Powering ARM-based application processors and LPDDR3 memory in 10″ Android tablets with aggressive battery life targets. IC Role / Device Role / Timing Role: Adaptive-frequency buck controller leveraging ULQ™ mode during suspend-to-RAM and D-CAP™ for rapid wake-up transients. Use Value: Achieves >92% efficiency at 100 mA load (CH1+CH2) and <25 µA quiescent draw-extending standby time beyond 21 days. |
Use Scenario: Ruggedized industrial tablet requiring reliable 5 V/3.3 V rails under wide ambient (-25°C to 70°C) and input (9–24 V) variation. IC Role / Device Role / Timing Role: Dual-channel controller with non-latch OVP/UVP/OCP and -40°C to 85°C operation supporting extended temperature qualification. Use Value: Delivers fault recovery without host intervention (auto-retry on UVLO) and maintains ±1% output accuracy across full temperature range. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-buck controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS51285BRUKR | Always-on VREG5 (vs. EN-gated in TPS51285ARUKR); identical pinout, package, and control architecture. | Required where 5-V LDO must remain active during deep-sleep even if CH1 is disabled (e.g., always-on USB charging circuits). | Select TPS51285BRUKR when VREG5 availability independent of EN1/EN2 is mandatory; otherwise TPS51285ARUKR offers tighter system-level power gating. |
| RT8205AZSP | Single-chip dual buck + 5-V/3.3-V LDO; 500 kHz fixed frequency; no VCLK output; 40 V max VIN; different pin mapping. | Used in cost-sensitive consumer notebooks where charge-pump gate drive is unnecessary and higher VIN tolerance is needed. | Choose RT8205AZSP only if VCLK is unused and 40 V input capability is required; not drop-in due to pinout and control differences. |
Compared with TPS51285BRUKR, the TPS51285ARUKR provides finer system-level power control via EN-gated VREG5, while RT8205AZSP trades VCLK functionality and adaptive control for higher VIN rating and lower unit cost-making each suitable for distinct subsystem power architectures.
Availability
TPS51285ARUKR is available at Aetrix Electronics and suitable for notebook computers, tablet computers, and embedded industrial tablets requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for TPS51285ARUKR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in power management ICs for portable and industrial applications.
The TPS51285A product line was engineered specifically for high-efficiency, space-constrained system power in mobile computing-integrating dual buck control, LDOs, and intelligent protection into a single 3×3 mm QFN package.
FAQ
What is the key functional difference between TPS51285ARUKR and TPS51285BRUKR?
The TPS51285ARUKR gates its 5-V LDO (VREG5) using EN1/EN2 signals, meaning VREG5 activates only when at least one channel is enabled. In contrast, the TPS51285BRUKR provides an always-on VREG5 independent of EN states. Both share identical pinout, switching specs, and thermal performance-but TPS51285ARUKR enables deeper system-level power gating for longer battery standby.
Does TPS51285ARUKR support ceramic output capacitors in D-CAP™ mode?
No-TPS51285ARUKR's D-CAP™ loop stability requires output capacitors with sufficient ESR (≥10 mΩ), such as specialty polymer types. Ceramic capacitors typically exhibit too-low ESR (<2 mΩ), resulting in f0 > 700 kHz and potential instability. The datasheet explicitly recommends polymer or hybrid capacitors for stable operation.
How does the ULQ™ mode activate and what is its impact on TPS51285ARUKR operation?
ULQ™ mode activates automatically in TPS51285ARUKR when both high-side and low-side drivers are off during discontinuous conduction-reducing VIN supply current to 25 µA. All protections (OVP, UVP, OCP, OTP) remain fully active. The device exits ULQ™ when VFB drops to the 2-V reference, ensuring seamless transition to normal PWM operation without firmware intervention.
Can TPS51285ARUKR's VCLK output be disabled, and how?
Yes-TPS51285ARUKR's VCLK output is disabled by connecting a 200 Ω resistor from the VCLK pin to GND. This pulls the output low and disables the internal driver, eliminating unnecessary power draw and EMI when an external charge pump is not used. Leaving VCLK floating or unconnected may cause undefined behavior.
What is the purpose of the VO1 pin on TPS51285ARUKR beyond feedback sensing?
On TPS51285ARUKR, VO1 serves three critical roles beyond feedback: (1) it enables VREG5 switchover (connecting VREG5 to VO1 when conditions are met), (2) it provides the discharge path for the 5-V rail during shutdown via internal MOSFET, and (3) it feeds the VIN UVLO comparator for accurate 5-V rail monitoring-making it essential for safe power sequencing and fault recovery.
TPS51285ARUKR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- D-CAP™
- Package/Case:
- 20-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Topology:
- Step-Down (Buck) Synchronous (2), Linear (LDO) (2)
- Number of Outputs:
- 4
- Frequency - Switching:
- 400kHz, 475kHz
- Voltage/Current - Output 1:
- Controller
- Voltage/Current - Output 2:
- Controller
- Voltage/Current - Output 3:
- 3.3V, 100mA
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- No
- Voltage - Supply:
- 5V ~ 24V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-WQFN (3x3)
TPS51285ARUKR FAQ
1.How can I place an order for TPS51285ARUKR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS51285ARUKR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS51285ARUKR reliable?
The price and inventory of TPS51285ARUKR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS51285ARUKR is usually 5 days.
3.What payment methods are accepted for TPS51285ARUKR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS51285ARUKR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS51285ARUKR?
TPS51285ARUKR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS51285ARUKR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS51285ARUKR?
For technical support, including TPS51285ARUKR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS51285ARUKR requirements.
6.How does Aetrix verify that TPS51285ARUKR is sourced from the original manufacturer or authorized distributors?
All TPS51285ARUKR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS51285ARUKR meets industry standards.
7.What is the process for return or replacement of TPS51285ARUKR?
All TPS51285ARUKR units undergo pre-shipment inspection (PSI). If there is an issue with TPS51285ARUKR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS51285ARUKR part is unused and in its original packaging.
Return procedure for TPS51285ARUKR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TPS51285ARUKR Tags

-
TPS6521905RHBR
Texas Instruments

-
MIC3385YHL-TR
Microchip Technology

-
A4402ELPTR-T
Allegro MicroSystems
-
LM26480SQ-AA/NOPB
Texas Instruments

-
A4402KLPTR-T
Allegro MicroSystems

-
BD71847AMWV-E2
ROHM Semiconductor

-
ADP5040ACPZ-1-R7
Analog Devices Inc.

-
LT3048IDC#TRPBF
Analog Devices Inc.

-
ADP5037ACPZ-R7
Analog Devices Inc.

-
XRP7714ILB-F
MaxLinear, Inc.

-
LTC3260EDE#TRPBF
Analog Devices Inc.

-
LTC3260EMSE#PBF
Analog Devices Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
