Texas Instruments TPS5130PTG4

Overview

TPS5130PTG4 from Texas Instruments is a quad-output power management IC integrating three synchronous buck regulator controllers (SBRC) and one LDO controller for notebook PC and portable DSP power rails. It supports 4.5 V–28 V input, delivers 0.9 V–5.5 V adjustable switcher outputs and 0.9 V–2.5 V LDO output, features ±1.5% reference accuracy, 300–500 kHz PWM operation, and programmable overcurrent/overvoltage/undervoltage protection - deployed in multi-rail CPU core/I/O and peripheral voltage domains.

For engineers reviewing the TPS5130PTG4 datasheet, TPS5130PTG4 pinout, TPS5130PTG4 application, or TPS5130PTG4 equivalent, this page delivers verified functional architecture, validated terminal roles, confirmed thermal and electrical specifications per JEDEC PT package, and real-world design constraints including dead-time control (100 ns), auto PWM/SKIP mode transition, and FLT-latched fault recovery behavior.

Technical Context

The TPS5130PTG4 implements three independent SBRC channels with phase-shifted 180° operation to minimize input ripple and reduce bulk capacitance requirements. Each channel uses a high-speed error amplifier (2.5 MHz unity-gain bandwidth) with external FB/INV compensation, programmable current limit via TRIPx pins (13 µA typical), and integrated high-side (1.2 A sink/source) and low-side (1.5 A sink/source) N-MOSFET drivers.

Its fourth channel is an LDO controller driving an external N-channel MOSFET, featuring overshoot suppression (25 mA sink at LDO_OUT), 50 mV current-limit threshold, and shared FLT latching with SBRCs. Powergood monitoring covers all four outputs with ±7% tolerance and programmable delay via PG_DELAY capacitor.

Key Specifications

Pinout & Package

TPS5130PTG4 is housed in a 48-pin Plastic Thin Quad Flat Package (PT), thermally rated for −40°C to +85°C ambient operation and mounted on JEDEC high-k board (2 oz. surface traces, 2-layer 1 oz. internal plane).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar multi-rail power management applications.

Compared with TPS5130PTG4, TPS51461RGER offers higher current density but omits LDO functionality and analog control, while ISL95831IRZ adds digital control overhead and tighter Vref at the cost of reduced pin-level configurability and larger minimum layout footprint.

Availability

TPS5130PTG4 is available at Aetrix Electronics and suitable for notebook PC motherboard design, portable DSP power subsystems, and embedded industrial controller development requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for TPS5130PTG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in power management IC design for computing and portable electronics.

The TPS5130 product line was engineered specifically for multi-rail, battery-powered computing platforms - delivering tightly regulated, sequenced, and protected voltage domains with minimal external components and optimized thermal performance in compact PT packaging.

FAQ

What is the function of the CT pin on the TPS5130PTG4?

The CT pin on the TPS5130PTG4 connects to an external capacitor to ground and sets the oscillator frequency for the PWM triangle wave generator. With a 44 pF capacitor, the TPS5130PTG4 operates at 300 kHz; increasing capacitance lowers frequency. This directly determines switching frequency for all three SBRC channels and impacts inductor sizing, efficiency, and EMI profile in the final design.

How does the TPS5130PTG4 implement overcurrent protection for its buck channels?

The TPS5130PTG4 implements resistor-programmable overcurrent protection per buck channel using the TRIPx pins. An internal 13 µA current source flows through an external resistor tied between VIN_SENSE and TRIPx, generating a voltage threshold that compares against MOSFET R_DS(on) × I_OUT. When exceeded, the current comparator extends low-side conduction or terminates high-side pulses - triggering FLT latching if sustained. Temperature compensation (3400 ppm/°C) offsets MOSFET R_DS(on) drift.

Can the TPS5130PTG4's LDO controller drive a P-channel MOSFET instead of an N-channel device?

No - the TPS5130PTG4's LDO controller is designed exclusively for N-channel MOSFETs. Its LDO_GATE output is a source/sink driver referenced to LDO_IN, and the internal error amplifier and current limit comparator assume N-MOS topology with source tied to LDO_OUT. Driving a P-channel device would invert control polarity and disable current sensing via LDO_CUR, violating the specified operating architecture.

What is the purpose of the SS_STBYx pins on the TPS5130PTG4?

The SS_STBYx pins on the TPS5130PTG4 serve dual functions: soft-start control and standby enable for each SBRC channel. An internal current source charges an external capacitor connected to SS_STBYx, ramping voltage from 0 V to 0.85 V to linearly increase output voltage. Pulling SS_STBYx low disables the corresponding channel; tying it high enables immediate start. This allows independent sequencing and inrush current limiting per rail.

Does the TPS5130PTG4 support independent power-good assertion per output rail?

No - the TPS5130PTG4 features a single open-drain PGOUT pin that monitors all three SBRC outputs and the LDO output collectively. The PGOUT signal goes low if any monitored rail (via INVx or INV_LDO) deviates beyond ±7% of the 0.85 V reference. While PG_DELAY allows adjustment of propagation delay, there is no per-rail PG status; system-level monitoring must infer fault origin from auxiliary signals like FLT or individual soft-start completion.