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Texas Instruments TPS51313DRCR
- Part No.:
- TPS51313DRCR
- Manufacturer:
- Texas Instruments
- Package:
- 10-VFDFN Exposed Pad
- Datasheet:
-
TPS51313DRCR.pdf
- Description:
- IC REG BUCK ADJ 3A 10VSON
- Quantity:
- Payment:
- Shipping:
Inventory:4,605
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Product details
Overview
TPS51313DRCR from Texas Instruments is a fully integrated 3-A synchronous buck converter in a 3 mm × 3 mm VSON-10 (DRC) package, designed for low-voltage point-of-load applications. It operates from 3.1 V to 5.5 V input, delivers 0.6 V to 3.3 V output with 1% reference accuracy, and uses D-CAP2™ adaptive constant-on-time control at 1 MHz for fast transient response in discrete graphics PCIe® PEX rail systems.
For engineers reviewing the TPS51313DRCR datasheet, TPS51313DRCR pinout, TPS51313DRCR application, or TPS51313DRCR equivalent, key selection criteria include its no-external-compensation design, integrated high-side/low-side FETs, auto-skip light-load efficiency, pre-biased startup, and thermal shutdown with 20°C hysteresis - all validated for –10°C to 85°C industrial operation.
Technical Context
The TPS51313DRCR implements D-CAP2™ control architecture with an internal integrator and three-loop PWM operation: internal current sensing at the SW node, voltage feedback via FB pin referenced to 0.6-V bandgap, and fast feedforward modulation of on-time during load transients. Its valley-current limit is fixed at 4.8 A, and it features programmable soft-start (300 µs), open-drain PGOOD with 1.3-ms delay, and dual UVLO monitoring on VIN and VCC (2.95 V wake-up, 2.7 V shutdown).
Protection logic includes latched OVP (130% VREF), UVP (50% VREF), overcurrent (9-cycle latch-off), and non-latched thermal shutdown at 145°C. The device supports pre-biased output startup and discharges the output capacitor through an internal resistor when disabled - critical for multi-rail sequencing in GPU power delivery.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 3.1 V to 5.5 V - supports both 3.3-V and 5-V system rails without external level-shifting. |
| Output Voltage Range | 0.6 V to 3.3 V - set by external R1/R2 divider; 0.6-V ±1% reference enables precise POL regulation. |
| Max Output Current | 3 A DC - monolithically integrates high-side and low-side FETs; no external MOSFETs required. |
| Switching Frequency | 1 MHz - enables compact all-ceramic designs with small inductors (e.g., 0.56 µH) and minimal footprint. |
| Control Mode | D-CAP2™ adaptive constant-on-time - eliminates external compensation, provides <100-ns transient response, and auto-skips at light load. |
| Soft-Start Time | 300 µs - fixed internal ramp from 0 V to 0.6 V reference; ensures controlled VOUT rise without inrush current. |
| Thermal Shutdown | 145°C threshold with 20°C hysteresis - non-latched recovery allows automatic restart after cooling, improving system resilience. |
Pinout & Package
The TPS51313DRCR is housed in a 3 mm × 3 mm, 10-pin VSON (DRC) package with exposed thermal pad soldered to PGND for optimal thermal performance (θJCbot = 6.3°C/W). Pin 1 is located in Quadrant Q2 per tape-and-reel orientation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| FB (Pin 1) | Voltage feedback input | Monitors output via resistor divider; sets regulation point and triggers PGOOD, OVP (130% VREF), and UVP (50% VREF). |
| VCC (Pin 2) | Analog supply rail | Provides bias for internal circuitry; monitored for UVLO (2.95 V wake-up); must be ≥3.1 V for full functionality. |
| VIN (Pin 3) | Main power input | Supplies gate drive for internal FETs and power conversion path; shares UVLO monitoring with VCC. |
| PGND (Pins 4, 5) | Power ground return | Dual pins reduce IR drop and improve thermal conduction; must connect directly to thermal pad and PCB ground plane. |
| EN (Pin 10) | Enable control input | 3.3-V logic compatible (VIL = 0.8 V, VIH = 1.5 V); initiates soft-start and disables output discharge path when low. |
| PGOOD (Pin 9) | Open-drain status output | Asserts after 1.3-ms delay post-EN high; deasserts on fault (UVLO, OVP, UVP, OCP, thermal); requires external 100-kΩ pull-up. |
| NC (Pin 8) | No-connect terminal | Internally unconnected; must remain floating - no external trace or component allowed. |
| SW (Pins 6, 7) | Switch node outputs | Connects to external inductor; carries high di/dt switching current; dual pins reduce parasitic inductance and improve EMI. |
Key Features
| Feature | Design Value |
|---|---|
| No external compensation required | D-CAP2™ control with internal integrator zero (~60 kHz) ensures stability with standard MLCC output capacitors - eliminates tuning effort and BOM cost. |
| Pre-biased startup support | Allows safe turn-on when output capacitor is pre-charged (e.g., in multi-phase or hot-swap systems), preventing reverse current flow into the IC. |
| Auto-skip mode at light load | Disables low-side FET conduction when inductor current goes negative, reducing switching losses and maintaining >85% efficiency at 10-mA loads. |
| Integrated output capacitor discharge | Internal resistor actively discharges VOUT when EN is low - essential for clean power-down sequencing in GPU and FPGA applications. |
| Fixed 300-µs soft-start | Guarantees monotonic VOUT ramp with no external components; prevents overshoot and reduces stress on downstream capacitors and ICs. |
Applications
| Discrete Graphics PCIe® PEX Rail | Low-Voltage Point-of-Load (POL) |
|---|---|
Use Scenario: Powering NVIDIA GPU core voltage (e.g., 1.05 V @ 3 A) in desktop/workstation graphics cards compliant with OpenVreg Type 0 spec. IC Role / Device Role / Timing Role: Primary DC-DC regulator delivering tightly regulated, fast-transient-responsive bias rail synchronized to PCIe slot power sequencing. Use Value: Meets NVIDIA OpenVreg timing requirements (e.g., 300-µs soft-start, 1.3-ms PGOOD delay) and supports 2.5-A/µs di/dt transients without droop exceeding ±3%. | Use Scenario: Generating sub-1.2-V core supplies for ASICs, FPGAs, or SoCs in industrial embedded controllers where space and thermal density are constrained. IC Role / Device Role / Timing Role: Standalone POL converter replacing multi-component discrete solutions; handles dynamic load steps up to 3 A with <100-ns response latency. Use Value: Achieves >92% peak efficiency at 1.05 V/3 A using only ceramic capacitors and a 0.56-µH inductor - enabling 1.2-mm max height power stages. |
| GPU Memory Interface Rails | Multi-Rail Sequencing Systems |
Use Scenario: Supplying GDDR6/GDDR6X memory termination or I/O voltage (e.g., 1.35 V) in AI accelerators requiring tight voltage tolerance and low noise. IC Role / Device Role / Timing Role: Secondary POL regulator with independent enable control; coordinated via EN pin to match memory initialization timing windows. Use Value: 0.6-V ±1% reference and 1% total output error (including line/load regulation) ensure compliance with JEDEC memory voltage specs under full temperature range. | Use Scenario: Managing power-up/down sequencing across CPU, GPU, and memory rails in edge AI servers using discrete enable signals and PGOOD handshaking. IC Role / Device Role / Timing Role: Sequenced POL node with programmable startup delay (via RC on EN) and fault-signaling PGOOD output for system-level supervision. Use Value: Internal discharge path and latched fault behavior (OVP/UVP/OCP) prevent bus contention and enable deterministic reset recovery without external supervisors. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS51317DRCR | Same DRC package, 3-A rating, but supports 1.5-MHz switching and wider 0.6–5.5-V output range; lacks PGOOD pin. | Omits power-good signaling - unsuitable for systems requiring fault reporting or sequencing coordination. | Select when higher frequency (1.5 MHz) and extended output range are prioritized over PGOOD functionality. |
| MP2315DJ-LF-Z | Monolithic 3-A buck in 8-pin SOIC-EP; 2.5–5.5-V input; 0.8–5-V output; 500-kHz fixed frequency; no PGOOD or UVLO on VCC. | Lacks dual UVLO monitoring and integrated discharge path - requires external circuitry for robust multi-rail sequencing. | Choose for cost-sensitive, non-sequencing applications where SOIC thermal performance suffices and PGOOD is not required. |
Compared with TPS51313DRCR, TPS51317DRCR trades PGOOD for higher frequency and broader output flexibility, while MP2315DJ-LF-Z offers lower BOM cost but sacrifices sequencing reliability and thermal efficiency due to larger package and absence of key protection features.
Availability
TPS51313DRCR is available at Aetrix Electronics and suitable for discrete graphics PCIe® PEX rail, low-voltage point-of-load (POL), and GPU memory interface applications requiring stable component supply, long-term industrial temperature support (–10°C to 85°C), and RoHS-compliant green packaging.
Supply support for TPS51313DRCR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-efficiency DC-DC conversion.
The TPS51313DRCR belongs to TI's OpenVreg-compliant POL converter product line, engineered specifically for NVIDIA GPU power delivery and PCIe graphics card applications demanding tight regulation, fast transient response, and seamless integration with industry-standard power architectures.
FAQ
What is the maximum continuous output current supported by the TPS51313DRCR?
The TPS51313DRCR supports a maximum continuous DC output current of 3 A, enabled by its monolithically integrated high-side and low-side MOSFETs. This rating is validated across the full operating temperature range (–10°C to 85°C) with proper PCB thermal design - including connection of the exposed thermal pad to a solid PGND plane - and assumes use of recommended external components (e.g., 0.56-µH inductor, 66-µF MLCC output capacitance).
Does the TPS51313DRCR require external compensation components?
No, the TPS51313DRCR does not require external compensation components. Its D-CAP2™ adaptive constant-on-time control architecture incorporates an internal integrator with a zero placed at ~60 kHz, ensuring inherent stability with standard ceramic output capacitors. This eliminates the need for external RC networks, simplifying layout and reducing BOM count - a key advantage confirmed in the SLUSB31 datasheet Section 8.2.2.
How does the TPS51313DRCR handle power-down sequencing?
When the EN pin is pulled low, the TPS51313DRCR actively discharges the output capacitor through an internal resistor, ensuring controlled VOUT ramp-down. This feature prevents back-driving of upstream sources or downstream devices during power-down - critical for reliable multi-rail sequencing in GPU and FPGA systems. The discharge path remains active until VOUT falls below the UVP threshold (50% × 0.6 V), at which point the device latches off.
What protection features are integrated into the TPS51313DRCR?
The TPS51313DRCR integrates six key protections: (1) Input UVLO on both VIN and VCC (2.95 V wake-up, 2.7 V shutdown), (2) Output OVP (130% VREF, 1.9-µs delay), (3) Output UVP (50% VREF, 2.4-µs delay), (4) Overcurrent protection (4.8-A valley limit, 9-cycle latch-off), (5) Thermal shutdown (145°C, 20°C hysteresis), and (6) PGOOD fault signaling. All are documented in Sections 7.1–7.6 of the SLUSB31 datasheet.
Can the TPS51313DRCR operate with a pre-biased output voltage?
Yes, the TPS51313DRCR supports pre-biased startup - meaning it can safely begin regulation even when the output capacitor is already charged to a non-zero voltage. This capability prevents reverse current flow into the IC during hot-swap or multi-phase turn-on scenarios. The device achieves this via internal circuitry that monitors SW node voltage and disables low-side FET conduction until the output reaches regulation, as detailed in Section 8.3.7 of the SLUSB31 datasheet.
TPS51313DRCR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- D-CAP2™
- Package/Case:
- 10-VFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 3.1V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.6V
- Voltage - Output (Max):
- 3.3V
- Current - Output:
- 3A
- Frequency - Switching:
- 1MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -10°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-VSON (3x3)
TPS51313DRCR FAQ
1.How can I place an order for TPS51313DRCR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS51313DRCR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS51313DRCR reliable?
The price and inventory of TPS51313DRCR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS51313DRCR is usually 5 days.
3.What payment methods are accepted for TPS51313DRCR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS51313DRCR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS51313DRCR?
TPS51313DRCR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS51313DRCR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS51313DRCR?
For technical support, including TPS51313DRCR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS51313DRCR requirements.
6.How does Aetrix verify that TPS51313DRCR is sourced from the original manufacturer or authorized distributors?
All TPS51313DRCR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS51313DRCR meets industry standards.
7.What is the process for return or replacement of TPS51313DRCR?
All TPS51313DRCR units undergo pre-shipment inspection (PSI). If there is an issue with TPS51313DRCR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS51313DRCR part is unused and in its original packaging.
Return procedure for TPS51313DRCR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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