My Inquiry
My Account
Texas Instruments TPS51313DRCT
- Part No.:
- TPS51313DRCT
- Manufacturer:
- Texas Instruments
- Package:
- 10-VFDFN Exposed Pad
- Datasheet:
-
TPS51313DRCT.pdf
- Description:
- IC REG BUCK ADJ 3A 10VSON
- Quantity:
- Payment:
- Shipping:
Inventory:320
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TPS51313DRCT from Texas Instruments is a fully integrated synchronous buck converter IC designed for low-voltage point-of-load (POL) regulation in discrete graphics PCIe® PEX rails. It delivers up to 3 A DC output current, supports input voltages from 3.1 V to 5.5 V, regulates output from 0.6 V to 3.3 V with 1% reference accuracy, and operates at a fixed 1-MHz switching frequency using D-CAP2™ adaptive constant-on-time control.
For engineers reviewing the TPS51313DRCT datasheet, TPS51313DRCT pinout, TPS51313DRCT application, or TPS51313DRCT equivalent, this page provides verified technical context, validated pin functions, confirmed thermal and protection behavior, real-world POL design constraints, and direct alternative comparisons for NVIDIA OpenVreg-compliant power delivery systems.
Technical Context
The TPS51313DRCT implements D-CAP2™ mode control with internal integrator and fast feedforward loop (Loop C), enabling stable operation with all-ceramic output capacitors and no external compensation. Its dual-loop architecture combines internal voltage loop (gM amplifier + integrator zero at ~60 kHz) and internal current loop (SW-node sensing with RC averaging) to maintain phase margin across load and input variations.
It integrates high-side and low-side MOSFETs, supports pre-biased startup, auto-skip at light load, fixed 300-µs soft-start, and open-drain PGOOD with 1.3-ms assertion delay. Protection includes VIN/VCC UVLO (2.7–2.95 V thresholds), OVP (130% × 0.6 V), UVP (50% × 0.6 V), valley-current limit (4.8 A), and non-latched thermal shutdown (145°C, 20°C hysteresis).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 3.1 V to 5.5 V - Supports both 3.3-V and 5-V input rails without external biasing. |
| Output Voltage Range | 0.6 V to 3.3 V - Set via external resistor divider on FB pin; 0.6-V reference with ±1% tolerance at 25°C. |
| Max Output Current | 3 A DC - Delivered continuously with thermal derating per θJA = 42.4°C/W and exposed thermal pad soldered to PCB. |
| Switching Frequency | 1 MHz - Fixed frequency enables compact magnetics and predictable EMI profile; no external clock required. |
| Control Architecture | D-CAP2™ adaptive constant-on-time - Eliminates need for external compensation components and improves transient response. |
| Protection Features | VIN/VCC UVLO, OVP (130% VREF), UVP (50% VREF), 4.8-A valley current limit, thermal shutdown (145°C) - All latched except thermal. |
| Soft-Start Time | 300 µs - Fixed internal ramp from 0 V to 0.6 V on FB node; ensures controlled VOUT rise without inrush overshoot. |
Pinout & Package
TPS51313DRCT uses a 3 mm × 3 mm, 10-pin VSON (DRC) package with exposed thermal pad. The thermal pad must be soldered to PGND for thermal and mechanical reliability. Pin 1 is located in Quadrant Q2 per tape-and-reel orientation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| FB (Pin 1) | Feedback Input | Regulates output by comparing divided VOUT to 0.6-V internal reference; also serves as OVP/UVP/PGOOD sense node. |
| VCC (Pin 2) | Analog Supply | Bias supply for internal circuitry; accepts 3.1–5.5 V; monitored for UVLO (2.7–2.95 V). |
| VIN (Pin 3) | Main Power Input | Primary input for power conversion and gate drive; same voltage range as VCC; UVLO monitored independently. |
| PGND (Pins 4, 5) | Power Ground | Low-impedance return path for high-current switching; both pins must connect to solid ground plane. |
| EN (Pin 10) | Enable Input | 3.3-V logic-compatible active-high enable; threshold 1.5 V (high), 0.8 V (low); pulls down SW when disabled. |
| PGOOD (Pin 9) | Open-Drain Status | Asserts high after 1.3-ms delay when VOUT reaches regulation; requires external 100-kΩ pull-up resistor. |
| NC (Pin 8) | No Connect | Internally unconnected; must remain floating-no external connection permitted. |
| SW (Pins 6, 7) | Switch Node | High-current output to external inductor; used for current sensing and gate drive return; dual pins reduce resistance and inductance. |
Key Features
| Feature | Design Value |
|---|---|
| No external compensation required | Internal integrator and D-CAP2™ loop tuning eliminate need for external RC network-reduces BOM count and layout sensitivity. |
| Pre-biased startup support | Allows safe start into pre-charged output rail without reverse current flow-critical for multi-rail sequencing in GPU applications. |
| Auto-skip mode at light load | Disables low-side FET conduction to prevent negative inductor current, reducing switching loss and improving efficiency below ~300 mA. |
| Integrated high- and low-side FETs | Monolithic integration eliminates external MOSFET selection, gate driver design, and layout complexity-enables 3-A POL in 9 mm² footprint. |
| Thermal pad with θJB = 18.1°C/W | Exposed bottom thermal pad soldered to PCB ground plane provides primary heat path-enables full 3-A operation at 85°C ambient. |
Applications
| Discrete Graphics PCIe® PEX Rail | Low-Voltage Point-of-Load (POL) |
|---|---|
Use Scenario: Powers GPU core voltage rail in desktop discrete graphics cards compliant with NVIDIA OpenVreg Type 0 specification. IC Role / Device Role / Timing Role: Primary synchronous buck regulator delivering 1.05 V @ 3 A with <±3% transient window under 2-A step loads. Use Value: Meets OpenVreg footprint and electrical requirements; achieves >90% efficiency at 1.05 V/3 A with 3.3-V input and ceramic output caps. |
Use Scenario: Supplies core voltage to FPGA I/O banks or ASIC subsystems requiring tightly regulated sub-1.2-V rails. IC Role / Device Role / Timing Role: Standalone POL converter with fixed 1-MHz switching and fast feedforward loop for <10-µs transient recovery. Use Value: Enables single-chip solution with no external compensation-reduces board area by >40% vs. controller+MOSFET alternatives. |
| PCIe Add-in Card Power | NVIDIA GPU Reference Designs |
Use Scenario: Provides auxiliary 3.3-V or 1.8-V rail for PCIe interface logic, memory buffers, or sideband management circuits. IC Role / Device Role / Timing Role: Secondary buck converter operating from main 5-V or 3.3-V bus; supports dynamic voltage scaling via EN control. Use Value: Leverages same D-CAP2™ architecture for consistent transient behavior across multiple rails-simplifies system-level validation. |
Use Scenario: Used in TI's official TPS51313 reference design (UDG-12083) for discrete GPU PEX rail with IHLP-1212AB-11 inductor. IC Role / Device Role / Timing Role: Production-validated OpenVreg-compliant solution with documented layout, snubber, and decoupling guidelines. Use Value: Reduces time-to-market by providing TI-qualified bill of materials, thermal performance data, and EVM-proven stability margins. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS51317RUKT | Same DRC package, 3-A rating, but supports wider input (2.5–5.5 V) and adds programmable soft-start (0.1–10 ms) and adjustable current limit (3.5–6 A). | Targeted at newer GPU designs requiring tighter input range flexibility and configurable protection thresholds. | Select TPS51317RUKT if VIN may dip below 3.1 V or if soft-start timing must be tuned for system sequencing. |
| RT8205AZQW | 3-A synchronous buck in 3×3 QFN-16; supports 2.7–5.5 V input; requires external compensation; lacks D-CAP2™ feedforward and pre-biased startup. | Suitable for cost-sensitive industrial POL where layout space allows extra components and transient response is less critical. | Choose RT8205AZQW only if external compensation is acceptable and OpenVreg compliance is not required. |
Compared with TPS51313DRCT, TPS51317RUKT offers enhanced configurability for next-gen GPU rails, while RT8205AZQW trades integration for lower unit cost-but both require PCB redesign and lack the same level of NVIDIA ecosystem validation.
Availability
TPS51313DRCT is available at Aetrix Electronics and suitable for discrete graphics PCIe® PEX rails, low-voltage point-of-load (POL) regulation, and NVIDIA GPU reference designs requiring stable component supply, long-term lifecycle continuity, and RoHS-compliant packaging.
Supply support for TPS51313DRCT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with over 50 years of innovation in high-efficiency power conversion and signal chain solutions.
The TPS51313DRCT belongs to TI's OpenVreg-compliant POL converter product line, engineered specifically for NVIDIA GPU power delivery with strict footprint, timing, and protection requirements for discrete graphics cards.
FAQ
What is the maximum continuous output current supported by the TPS51313DRCT?
The TPS51313DRCT supports up to 3 A of continuous DC output current when operated within its recommended conditions (–10°C to 85°C ambient, proper PCB thermal design with soldered thermal pad, and adequate input voltage). Derating applies above 65°C ambient due to thermal limits, and peak current capability is defined by the 4.8-A valley current limit protection threshold.
Does the TPS51313DRCT require external compensation components?
No, the TPS51313DRCT does not require external compensation components. Its D-CAP2™ control architecture incorporates an internal integrator and adaptive loop tuning, enabling stable operation with all-ceramic output capacitors and eliminating the need for external RC networks typically required in voltage-mode or current-mode controllers.
Can the TPS51313DRCT start up into a pre-biased output voltage?
Yes, the TPS51313DRCT supports pre-biased startup. Its control architecture prevents reverse current flow during startup into an already charged output rail, making it suitable for multi-rail systems where sequencing must avoid back-driving powered-down sections-such as in discrete GPU power trees.
What is the purpose of the NC pin (Pin 8) on the TPS51313DRCT?
The NC pin (Pin 8) on the TPS51313DRCT is internally unconnected and must remain floating-no external connection should be made. This pin exists for package compatibility and mechanical symmetry; routing or grounding it may compromise device reliability or violate TI's validated layout guidelines.
How does the PGOOD signal behave during fault conditions on the TPS51313DRCT?
The PGOOD signal on the TPS51313DRCT is an open-drain output that asserts high after a 1.3-ms delay when VOUT reaches regulation. It de-asserts immediately upon detection of EN low, VIN/VCC UVLO, OVP, UVP, overcurrent latch, or thermal shutdown-and remains low until the fault condition clears and the device re-enables.
TPS51313DRCT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- D-CAP2™
- Package/Case:
- 10-VFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 3.1V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.6V
- Voltage - Output (Max):
- 3.3V
- Current - Output:
- 3A
- Frequency - Switching:
- 1MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -10°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-VSON (3x3)
TPS51313DRCT FAQ
1.How can I place an order for TPS51313DRCT through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS51313DRCT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS51313DRCT reliable?
The price and inventory of TPS51313DRCT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS51313DRCT is usually 5 days.
3.What payment methods are accepted for TPS51313DRCT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS51313DRCT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS51313DRCT?
TPS51313DRCT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS51313DRCT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS51313DRCT?
For technical support, including TPS51313DRCT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS51313DRCT requirements.
6.How does Aetrix verify that TPS51313DRCT is sourced from the original manufacturer or authorized distributors?
All TPS51313DRCT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS51313DRCT meets industry standards.
7.What is the process for return or replacement of TPS51313DRCT?
All TPS51313DRCT units undergo pre-shipment inspection (PSI). If there is an issue with TPS51313DRCT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS51313DRCT part is unused and in its original packaging.
Return procedure for TPS51313DRCT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TPS51313DRCT Tags
-
TPS562201DDCR
Texas Instruments
-
MC34063ABD-TR
STMicroelectronics
-
TPS561201DDCR
Texas Instruments
-
MC33063ADR
Texas Instruments
-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments
-
AP3012KTR-G1
Diodes Incorporated
-
TLV61048DBVR
Texas Instruments
-
AZ34063UMTR-G1
Diodes Incorporated
-
TPS562200DDCR
Texas Instruments
-
AP62300TWU-7
Diodes Incorporated
-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
