Texas Instruments TPS51362RVET

Overview

TPS51362RVET from Texas Instruments is a 22-V input, 10-A synchronous step-down DC/DC converter with integrated high- and low-side FETs, ULQ™ ultra-low quiescent current mode (100 µA), D-CAP2™ adaptive on-time control, and 800 kHz fixed switching frequency - designed for DDR memory VDDQ and notebook VCCIO rails.

For engineers reviewing the TPS51362RVET datasheet, TPS51362RVET pinout, TPS51362RVET application, or TPS51362RVET equivalent, this device delivers precise 0.6–2.0 V output regulation with differential voltage sensing, programmable overcurrent limit (8 A or 12 A), integrated power-good signaling, and thermal shutdown protection in a compact 3.5 mm × 4.5 mm QFN package.

Technical Context

The TPS51362RVET implements TI's D-CAP2™ architecture, using internal phase compensation (dual 8 kHz zeros) and an integrator formed by the SLEW pin capacitor to enable stable operation with all-MLCC or POSCAP output capacitors - eliminating external compensation components. Its adaptive on-time control dynamically adjusts t_ON based on input voltage, output voltage, and load conditions to maintain constant frequency under varying line/load.

ULQ™ mode is activated via the LP# pin and reduces quiescent current to 100 µA while preserving full functionality including soft-start, PGOOD assertion, and fault monitoring - critical for system standby battery life. Overcurrent protection uses valley-current sensing at the SW node with dual OCL thresholds set by the TRIP pin (GND = 8 A, 5 V = 12 A), and negative OCL is enforced during OOB/OVP discharge cycles.

Key Specifications

Pinout & Package

TPS51362RVET is housed in a 28-pin, 3.5 mm × 4.5 mm, 0.4-mm pitch QFN package (RVE) with exposed thermal pad. The package supports high-density PCB layouts and provides low thermal resistance (θ_JA = 40.2°C/W, θ_JCbot = 2.2°C/W).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous buck converter applications.

Compared with TPS51362RVET, TPS51367RVET adds CPU-specific features at higher cost and complexity, while ISL95831IRZ trades integration for configurability - making TPS51362RVET the optimal choice for fixed-output, low-quiescent DDR memory power delivery.

Availability

TPS51362RVET is available at Aetrix Electronics and suitable for notebook VCCIO, DDR VDDQ, FPGA I/O bank, and embedded GPU core logic applications requiring stable component supply, long-term lifecycle support, and consistent parametric performance.

Supply support for TPS51362RVET includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in high-efficiency DC/DC conversion and notebook power architecture.

The TPS51362RVET belongs to TI's high-voltage, integrated-FET buck converter product line - engineered specifically for DDR memory and notebook I/O rail applications demanding ultra-low quiescent current, minimal external components, and robust fault protection.

FAQ

What is the minimum input voltage required for TPS51362RVET to operate?

The TPS51362RVET operates with a minimum input voltage of 3 V, as specified in the Recommended Operating Conditions table. Below this threshold, the internal bias circuitry cannot sustain regulation, and UVLO on the V5 supply may trigger shutdown. For reliable startup and continuous operation across temperature, maintain VIN ≥3.3 V with adequate margin.

How does the ULQ™ mode affect PGOOD behavior in TPS51362RVET?

In ULQ™ mode (activated by pulling LP# low), the TPS51362RVET maintains full PGOOD functionality: it asserts after the programmed soft-start period plus 1.5 ms delay once VOUT reaches within ±8% of the target, and de-asserts immediately on OVP (>120%) or UVP (<68%). The 100 µA quiescent current does not compromise fault detection latency or sequencing integrity.

Can TPS51362RVET support all-MLCC output capacitors without external compensation?

Yes - the TPS51362RVET's D-CAP2™ architecture is explicitly designed for stable operation with all-MLCC output configurations. Its internal phase compensation network (dual 8 kHz zeros) and SLEW-based integrator eliminate the need for external RC networks, enabling fast transient response and reduced BOM count for DDR memory rails.

What is the purpose of the GSNS pin in TPS51362RVET, and how should it be connected?

The GSNS pin provides the ground reference for differential voltage sensing. It must be connected to the system ground plane near the load or to the remote ground point of the output capacitor to reject PCB trace IR drop. Connecting GSNS directly to the PGND pad defeats the benefit of differential sensing and degrades load regulation accuracy.

How is the soft-start time determined for TPS51362RVET, and what capacitor value yields ~1 ms for a 1.05-V output?

The soft-start time is set by the SLEW pin capacitor: t_SS ≈ (C_SLEW × V_OUT) / 10 µA. For a 1.05-V output and 1 ms target, C_SLEW = (10 µA × 1 ms) / 1.05 V ≈ 9.5 nF - a standard 10 nF ceramic capacitor achieves this. Larger values increase soft-start duration linearly and reduce inrush current stress.