Texas Instruments TPS51367RVET
- Part No.:
- TPS51367RVET
- Manufacturer:
- Texas Instruments
- Package:
- 28-VFQFN Exposed Pad
- Datasheet:
-
TPS51367RVET.pdf
- Description:
- IC REG BUCK ADJ 12A 28VQFN
- Quantity:
- Payment:

- Shipping:

Inventory:884
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Product details
Overview
TPS51367RVET from Texas Instruments is a 22-V input, 12-A synchronous step-down DC/DC converter with integrated high- and low-side FETs, D-CAP2™ control architecture, ULQ™ ultra-low quiescent current mode (100 µA), and 0.6–2.0 V programmable output voltage - designed for DDR memory VDDQ and notebook VCCIO rails.
For engineers reviewing the TPS51367RVET datasheet, TPS51367RVET pinout, TPS51367RVET application, or TPS51367RVET equivalent, this page delivers verified technical context, validated pin functions, confirmed thermal and protection behavior, and real-world design implications for battery-sensitive point-of-load systems.
Technical Context
The TPS51367RVET implements adaptive on-time D-CAP2™ control with internal phase compensation (60 µS gM amplifier + SLEW capacitor integrator), enabling stable operation with all-MLCC or POSCAP output capacitors without external compensation. It supports auto-skip light-load mode and zero-crossing detection to prevent negative inductor current.
Switching frequency is selectable between 400 kHz and 800 kHz via the MODE pin; overcurrent limit is programmable (7–18 A) using the TRIP pin; and output voltage is set either by resistor divider (REFIN/REFIN2) or fixed values (1.05 V, 1.2 V, 1.35 V, 1.5 V). Protection includes OCL, OVP (120% typ), UVP (66% typ), thermal shutdown (140°C), and non-latching 5-V UVLO.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 3 V to 22 V - supports wide-input notebook and industrial POL applications without pre-regulation. |
| Output Current Rating | 12 A continuous - enables single-chip solution for DDR3/DDR4 VDDQ rails up to 6 GB modules. |
| Quiescent Current (ULQ™) | 100 µA at LP# active - extends system standby battery life in ultrabooks and mobile platforms. |
| Switching Frequency | 400 kHz or 800 kHz (MODE-pin selectable) - balances inductor size (0.33 µH @ 800 kHz) vs. efficiency (peak >90% @ 12 A). |
| Output Voltage Range | 0.6 V to 2.0 V - covers DDR3 VDDQ (1.5 V), DDR4 VDDQ (1.2 V), LPDDR4 (1.1 V), and Intel VCCIO (1.05 V). |
| Thermal Shutdown Threshold | 140°C with 10°C hysteresis - ensures safe operation under sustained 12-A load in 3.5 mm × 4.5 mm QFN package. |
| Protection Features | OCL (valley-current sensing), OVP (120% typ), UVP (66% typ), UVLO (4.0 V typ), thermal shutdown - full fault coverage without external circuitry. |
Pinout & Package
TPS51367RVET uses a 28-pin, 3.5-mm × 4.5-mm, 0.4-mm pitch RVE QFN package with exposed thermal pad (PGND-connected). Package height is 1 mm, rated for –10°C to +85°C ambient operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| EN (Pin 28) | Enable input | 1.05-V logic-compatible enable; asserts converter only when pulled above 0.9 V with ≥0.25 V hysteresis. |
| LP# (Pin 2) | Low-power mode control | Active-low signal entering ULQ™ mode; reduces IQ to 100 µA while maintaining regulation during system sleep. |
| REFIN / REFIN2 (Pins 25/24) | Output voltage setpoint inputs | Dual-pin encoding selects fixed outputs (1.05 V, 1.2 V, 1.35 V, 1.5 V) or enables 0.6–2.0 V resistor-divider programming. |
| SLEW (Pin 21) | Soft-start/integrator node | Connects to GND via external capacitor (e.g., 10 nF) to set soft-start time (tSS = VOUT × CSLEW / 10 µA). |
| TRIP (Pin 20) | Overcurrent limit programming | GND = 8 A, 5 V = 12 A, FLOAT = 16 A - sets valley-current OCL threshold without external sense resistor. |
| VSNS / GSNS (Pins 22/23) | Differential output voltage sensing | VSNS monitors VOUT; GSNS connects to system ground return - enables accurate remote sensing and load-line regulation. |
| BST (Pin 5) | Bootstrap supply | Drives high-side FET gate; requires 0.1-µF ceramic capacitor to SW for proper bootstrap charging. |
| VREF (Pin 26) | 2.0-V reference output | Stable 2.0 V ±1% reference with 300 µA sourcing capability - used for precision feedback divider biasing. |
Key Features
| Feature | Design Value |
|---|---|
| D-CAP2™ adaptive on-time control | Enables stable loop response with all-MLCC output caps - eliminates need for external compensation network. |
| ULQ™ ultra-low quiescent current mode | Reduces operating IQ to 100 µA during LP# assertion - critical for >1-week battery standby in modern notebooks. |
| Integrated FET power stage | 15 mΩ high-side + 7.5 mΩ low-side RDS(on) - achieves >90% peak efficiency at 12 A without discrete MOSFETs or drivers. |
| Programmable switching frequency | 400 kHz or 800 kHz selection via MODE pin - allows trade-off between inductor size (0.33 µH @ 800 kHz) and EMI performance. |
| Valley-current OCL with TRIP pin | Three OCL thresholds (8 A / 12 A / 16 A) set by single TRIP pin voltage - simplifies current-limit tuning across board variants. |
| Differential remote sensing (VSNS/GSNS) | Compensates for PCB trace IR drop - maintains ±0.5% output accuracy under dynamic load steps up to 12 A. |
Applications
| DDR Memory Power Delivery | Notebook VCCIO Rail |
|---|---|
Use Scenario: Powers DDR3/DDR4 VDDQ rail in dual-channel memory subsystems requiring fast transient response and tight voltage tolerance. IC Role / Device Role / Timing Role: Primary synchronous buck regulator delivering regulated 1.2 V or 1.35 V with <1.5 ms PGOOD assertion and <100 ns OVP propagation delay. Use Value: D-CAP2™ control delivers <50 mV droop under 6-A/µs load step; integrated OCL prevents memory corruption during burst access. |
Use Scenario: Supplies Intel platform VCCIO (1.05 V) in ultrabook designs where battery life and board space are constrained. IC Role / Device Role / Timing Role: System-level POL converter with ULQ™ mode activated during S3/S4 sleep states to minimize system leakage. Use Value: 100 µA quiescent current extends standby runtime; 28-pin RVE package fits within 12 mm² footprint beside memory controller. |
| Industrial Embedded DDR Modules | Portable FPGA I/O Banks |
Use Scenario: Powers DDR interface on ruggedized ARM-based industrial controllers operating across –10°C to +85°C ambient. IC Role / Device Role / Timing Role: High-reliability DC/DC with thermal shutdown (140°C), non-latching UVLO, and 12-A continuous output for extended temperature operation. Use Value: Integrated power-good (PGOOD) with 1.5-ms startup delay ensures deterministic boot sequencing; PGND thermal pad sustains 12-A load at 85°C ambient. |
Use Scenario: Supplies configurable I/O bank voltage (1.2 V / 1.35 V / 1.5 V) for Xilinx/Intel FPGA development kits with multi-rail requirements. IC Role / Device Role / Timing Role: Flexible output voltage generator using REFIN/REFIN2 pin coding - eliminates need for external DAC or EEPROM configuration. Use Value: Four factory-programmed voltages reduce BOM count; SLEW-controlled soft-start prevents FPGA configuration failure during hot-plug events. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS51363RVET | Same RVE package and pinout; lacks ULQ™ mode (IQ = 300 µA min); fixed 800-kHz frequency only. | Not suitable for battery-critical standby modes; better for cost-sensitive, always-on industrial POLs. | Select when ULQ™ is unnecessary and higher light-load IQ is acceptable. |
| ISL95836IRZ | 12-A rating, 3–24 V input, but uses external MOSFETs; no integrated BST switch; requires external compensation. | Higher layout complexity and BOM count; supports wider VIN range and custom FET optimization. | Select when thermal headroom exceeds 28-pin QFN limits or discrete FET selection is required. |
Compared with TPS51367RVET, TPS51363RVET offers identical packaging and integration but sacrifices ULQ™ battery life extension, while ISL95836IRZ trades integration for flexibility in high-thermal or high-VIN designs - making TPS51367RVET optimal for space- and battery-constrained DDR POLs.
Availability
TPS51367RVET is available at Aetrix Electronics and suitable for notebook VCCIO, DDR VDDQ, and industrial embedded memory power applications requiring stable component supply, long-term lifecycle support, and TI-qualified production lots.
Supply support for TPS51367RVET includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in high-efficiency DC/DC conversion and notebook power architecture.
The TPS51367RVET belongs to TI's high-density POL converter product line, engineered specifically for DDR memory and CPU I/O rail applications demanding ultra-low IQ, fast transient response, and seamless integration into space-constrained mobile platforms.
FAQ
What is the maximum continuous output current supported by the TPS51367RVET?
The TPS51367RVET is rated for 12 A continuous output current under recommended operating conditions (TA ≤ 85°C, adequate PCB copper, 200 LFM airflow). Its integrated 15 mΩ high-side and 7.5 mΩ low-side FETs, combined with the 3.5 mm × 4.5 mm RVE package's 2.2°C/W θJCbot thermal resistance, enable this rating without external components. Derating applies above 85°C ambient or with natural convection only.
How does the ULQ™ mode function in the TPS51367RVET, and what triggers it?
The ULQ™ mode in the TPS51367RVET reduces quiescent current to 100 µA when the LP# pin is pulled low. This mode maintains regulation while minimizing bias current draw - essential for extending battery life during system standby (e.g., S3/S4 states). The TPS51367RVET exits ULQ™ automatically when LP# rises above 0.85 V, resuming full-performance operation without reset.
Can the TPS51367RVET operate with only MLCC output capacitors, and why?
Yes, the TPS51367RVET supports all-MLCC output configurations due to its D-CAP2™ control architecture, which uses an internal gM amplifier and SLEW capacitor integrator to synthesize phase compensation. This eliminates the need for high-ESR electrolytic or POSCAP capacitors - enabling compact, reliable, and low-profile designs ideal for thin notebooks and embedded DDR modules.
What are the valid output voltage options for the TPS51367RVET when using REFIN and REFIN2 pins?
The TPS51367RVET supports four fixed output voltages via REFIN and REFIN2 pin states: 1.05 V (both pins grounded), 1.2 V (REFIN2 grounded, REFIN floating), 1.35 V (both pins floating), and 1.5 V (REFIN grounded, REFIN2 floating). These settings are latched at startup; no reconfiguration occurs during operation unless EN is cycled.
Does the TPS51367RVET include output discharge functionality, and how is it implemented?
Yes, the TPS51367RVET provides controlled output discharge during shutdown. When EN is deasserted or a fault occurs, the low-side FET turns on actively to sink current from the output capacitor through the internal 7.5 mΩ RDS(on), discharging VOUT safely without external circuitry. Discharge rate depends on output capacitance and load, but the feature prevents floating or back-driving of downstream logic.
TPS51367RVET Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- D-CAP2™
- Package/Case:
- 28-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable (Programmable)
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 3V
- Voltage - Input (Max):
- 22V
- Voltage - Output (Min/Fixed):
- 0.6V (1.05V, 1.2V, 1.35V, 1.5V)
- Voltage - Output (Max):
- 2V
- Current - Output:
- 12A
- Frequency - Switching:
- 400kHz, 800kHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -10°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-VQFN-CLIP (4.5x3.5)
TPS51367RVET FAQ
1.How can I place an order for TPS51367RVET through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS51367RVET on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS51367RVET reliable?
The price and inventory of TPS51367RVET are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS51367RVET is usually 5 days.
3.What payment methods are accepted for TPS51367RVET?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS51367RVET transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS51367RVET?
TPS51367RVET orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS51367RVET order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS51367RVET?
For technical support, including TPS51367RVET datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS51367RVET requirements.
6.How does Aetrix verify that TPS51367RVET is sourced from the original manufacturer or authorized distributors?
All TPS51367RVET products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS51367RVET meets industry standards.
7.What is the process for return or replacement of TPS51367RVET?
All TPS51367RVET units undergo pre-shipment inspection (PSI). If there is an issue with TPS51367RVET, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS51367RVET part is unused and in its original packaging.
Return procedure for TPS51367RVET:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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