My Inquiry
My Account
Texas Instruments TPS5140PAG
- Part No.:
- TPS5140PAG
- Manufacturer:
- Texas Instruments
- Category:
- Special Purpose Regulators
- Package:
- 64-TQFP
- Datasheet:
-
TPS5140PAG.pdf
- Description:
- IC REG CTRLR NOTEBK 4OUT 64TQFP
- Quantity:
- Payment:
- Shipping:
Inventory:4,878
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TPS5140PAG from Texas Instruments is a quad-channel DC/DC controller integrating three synchronous-buck controllers (CH1–CH3) and one nonsynchronous 12-V boost converter, designed specifically for notebook PC peripheral power rails. It supports 4.5 V–28 V input, delivers adjustable step-down outputs down to 1.2 V, operates with PWM/SKIP mode auto-selection, and includes integrated 5-V and 3.3-V linear regulators (50 mA and 30 mA, respectively) - enabling compact, high-efficiency power management in space-constrained mobile platforms.
For engineers reviewing the TPS5140PAG datasheet, TPS5140PAG pinout, TPS5140PAG application, or TPS5140PAG equivalent, key selection considerations include per-channel standby control, programmable short-circuit protection via external TRIP resistors, independent soft-start timing per buck channel, 180° phase shift between CH1 and CH2/CH3 to reduce input ripple, and integrated gate drivers capable of 1.5 A sink/source for low-side and 1.2 A for high-side MOSFETs.
Technical Context
The TPS5140PAG implements voltage-mode PWM control with dedicated error amplifiers and skip comparators per buck channel, enabling stable regulation across load ranges. Its oscillator frequency (250 kHz typical, CT-tunable) governs all three buck channels, while CH2 and CH3 operate in-phase and CH1 operates 180° out-of-phase to minimize input capacitor requirements.
Protection architecture includes independent overvoltage (OVP: ±12% / –18% on INV pins) and undervoltage (UVP) monitoring per buck output, plus dedicated OVP/UVP for the 12-V boost stage. Fault response uses a shared SCP timer with differential charging current (5× higher for OVP vs UVP), latching all MOSFET drivers after programmable delay.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 4.5 V to 28 V - supports wide-input notebook adapter and battery supply without pre-regulation. |
| Buck Output Voltage Range | Adjustable down to 1.2 V - enables direct generation of core logic and I/O rail voltages (e.g., 3.3 V, 2.5 V, 1.8 V). |
| Oscillator Frequency | 250 kHz typical (CT-tunable) - balances efficiency, EMI, and component size for portable applications. |
| Gate Drive Capability | 1.5 A sink/source (low-side), 1.2 A sink/source (high-side) - drives low-rDS(on) N-channel MOSFETs without external buffers. |
| Linear Regulators | 5-V @ 50 mA and 3.3-V @ 30 mA - powers internal circuitry and auxiliary loads; both have separate standby control. |
| Power Good Delay | Programmable via external capacitor on PG_DELAY - allows precise sequencing alignment with system power-up timing. |
| Quiescent Current | 2.6 mA typical (active), <10 µA (shutdown) - extends battery life during light-load and standby operation. |
Pinout & Package
Packaged in a 64-pin TQFP (PAG) with exposed thermal pad, the TPS5140PAG features dedicated gate drive outputs (OUT1_u/OUT1_d through OUT3_u/OUT3_d), bootstrap terminals (LH1/LH2/LH3, LL1/LL2/LL3), and independent feedback (FB1/FB2/FB3), soft-start (SOFTSTART1/2/3), and standby (STBY1/STBY2/STBY3) pins per buck channel - enabling full channel isolation and flexible layout.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| FB1, FB2, FB3 | Feedback input for CH1–CH3 error amplifiers | Connects to resistor divider on each buck output to set regulated voltage; referenced to 1.185 V internal reference. |
| LH1/LH2/LH3 | Bootstrap capacitor connection for high-side gate drive | Provides floating bias for N-channel high-side MOSFET drivers; requires external 0.1-µF ceramic capacitor to OUT_x_u. |
| LL1/LL2/LL3 | Bootstrap return and current-sense node | Connects to source of low-side FET; used for current-limit sensing and floating driver return path. |
| TRIP1/TRIP2/TRIP3 | External current-limit programming input | Resistor-to-GND sets overcurrent threshold via internal 13 µA current source; enables precise per-channel OCP tuning. |
| STBY1/STBY2/STBY3 | Independent enable/disable control for CH1–CH3 | Logic-high enables channel; logic-low disables output and places drivers in high-impedance state - supports dynamic power gating. |
| PG_DELAY | Power good delay timing input | Capacitor-to-GND sets delay before PGOUT asserts; allows synchronization with downstream power rails or system reset timing. |
Key Features
| Feature | Design Value |
|---|---|
| Auto PWM/SKIP mode selection | Reduces light-load switching frequency and pulse width to extend battery life without compromising regulation at full load. |
| 180° phase shift between CH1 and CH2/CH3 | Cuts input ripple current by ~50%, allowing smaller, lower-cost bulk input capacitors in notebook power designs. |
| Dedicated 12-V boost converter with integrated NMOS | Delivers up to 120 mA at 12 V from 5-V input; includes OVP/UVP, soft-start, and phase compensation pin (PHASE_12V). |
| Programmable short-circuit protection (SCP) | Uses shared SCP timer with dual-source current (OVP = 5× UVP) to differentiate fault severity and prevent nuisance shutdowns. |
| Separate 5-V and 3.3-V linear regulators | Provide clean, low-noise bias for internal circuitry and external analog components; each has independent STBY control. |
Applications
| Notebook PC Peripheral Power | Mobile Embedded System Power |
|---|---|
|
Use Scenario: Powering USB ports, card readers, audio codecs, and display interface ICs in ultra-thin notebooks. IC Role / Device Role / Timing Role: Quad-channel controller generating 3.3 V, 2.5 V, 1.8 V, and 12 V rails from single 19-V adapter input with tight sequencing and fault isolation. Use Value: Eliminates need for four discrete controllers and external LDOs, reducing BOM count by >12 components and PCB area by ~35%. |
Use Scenario: Supplying multiple voltage domains in industrial handhelds with battery + adapter dual-input capability. IC Role / Device Role / Timing Role: Centralized power manager delivering sequenced, monitored, and independently controllable rails for ARM SoC, FPGA, and sensors. Use Value: Enables dynamic rail shutdown via STBY pins to cut system idle power by >40%, validated across –20°C to 85°C operating range. |
| PCMCIA/CardBus Power Supply | Multi-Rail Test Equipment Power |
|
Use Scenario: Providing isolated, protected 12-V supply for PCMCIA/ExpressCard hot-plug interfaces in legacy mobile workstations. IC Role / Device Role / Timing Role: Nonsynchronous 12-V boost converter (CH4) with LL_UP/IN_12V/OUT_12V pins driving external Schottky diode and inductor. Use Value: Meets PCMCIA 2.0 spec for 12-V rail (±5% tolerance, 120 mA max) with built-in OVP/UVP and soft-start - no external supervision IC required. |
Use Scenario: Generating calibrated, low-noise bias rails for benchtop signal generators and spectrum analyzers requiring rail stability <±0.5%. IC Role / Device Role / Timing Role: Precision reference source (1.185 V REF), combined with FB/INV inputs and PGOUT monitoring, enabling closed-loop calibration feedback. Use Value: REF tolerance (±1.5%) and PG comparator thresholds (±7%) support metrology-grade power validation without external references. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-rail DC/DC controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS51220ARSMR | Single 3-phase buck controller (no boost, no linear regs); supports VR12.5/IMVP-6; 300 kHz fixed freq. | Targeted at CPU core power only; lacks peripheral rail integration and 12-V boost capability. | Select when prioritizing CPU VDD rail efficiency over peripheral consolidation. |
| RT8205AZSP | Dual buck + dual LDO (no boost); 500 kHz switching; no per-channel phase control or SCP timer differentiation. | Designed for entry-level notebooks; missing 12-V boost, independent soft-start, and OVP/UVP hysteresis tuning. | Choose for cost-sensitive designs where 12-V peripheral power is supplied externally. |
Compared with TPS5140PAG, TPS51220ARSMR offers higher CPU rail efficiency but requires external 12-V generation and LDOs, while RT8205AZSP reduces cost at the expense of sequencing flexibility, fault discrimination, and boost functionality - making TPS5140PAG uniquely suited for full peripheral power integration in premium notebooks.
Availability
TPS5140PAG is available at Aetrix Electronics and suitable for notebook PC motherboard design, mobile embedded system power management, PCMCIA interface power, and multi-rail test equipment requiring stable component supply and long-term lifecycle support.
Supply support for TPS5140PAG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management solutions, with decades of expertise in high-reliability power IC design for computing and portable electronics.
The TPS5140 product line was engineered to consolidate notebook peripheral power delivery into a single IC - reducing solution size, improving efficiency across load conditions, and simplifying thermal and layout design for space-constrained mobile platforms.
FAQ
What is the function of the PWM_SEL pin on the TPS5140PAG?
The PWM_SEL pin on the TPS5140PAG selects between fixed PWM mode (logic low <0.5 V) and auto PWM/SKIP mode (logic high ≥2.5 V). In auto mode, the TPS5140PAG dynamically switches each buck channel to skip mode under light load to reduce switching losses and improve efficiency. This behavior is confirmed in the SLVS305A datasheet Section "auto PWM/SKIP" and verified in electrical characteristics tables.
Does the TPS5140PAG integrate MOSFETs, or does it require external power switches?
The TPS5140PAG does not integrate power MOSFETs; it is a controller IC requiring external N-channel high-side and low-side MOSFETs for each buck channel. The 12-V boost converter integrates an internal N-channel MOSFET, but all three synchronous-buck stages rely on external FETs driven by the TPS5140PAG's gate drivers (OUT1_u/d through OUT3_u/d). This is explicitly stated in the "description" section of the SLVS305A datasheet.
How is the 12-V boost output (OUT_12V) protected against overvoltage and undervoltage events?
The TPS5140PAG monitors the 12-V boost output using dedicated OVP and UVP comparators with thresholds of 12.9–13.9 V and 9–10 V, respectively. Upon detection, the SCP timer charges the external SCP capacitor; after the programmed delay, all MOSFET drivers (buck and boost) latch off. This dual-stage protection is detailed in the "OVP (12-V boost converter)" and "UVP (12-V boost converter)" subsections of the SLVS305A datasheet.
Can the TPS5140PAG generate a 1.2-V output for low-power logic circuits?
Yes, the TPS5140PAG supports adjustable step-down output voltages down to 1.2 V via resistor divider feedback on FB1, FB2, or FB3 pins. The internal 1.185 V reference (±1.5% tolerance) and voltage-mode error amplifier enable precise regulation at this level, as confirmed in the "detailed description" and "electrical characteristics" sections of the SLVS305A datasheet.
What is the purpose of the LL_UP and GND_UP pins on the TPS5140PAG?
LL_UP is the open-drain NMOS switch output for the 12-V boost converter, connecting between the external inductor and Schottky diode anode. GND_UP serves as the dedicated ground return for the 12-V boost circuitry. These pins isolate boost-stage grounding from buck-stage grounds, minimizing noise coupling - a requirement explicitly defined in the "Terminal Functions" table of the SLVS305A datasheet.
TPS5140PAG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 64-TQFP
- Packaging:
- Tray
- Product Status:
- Obsolete
- Applications:
- Controller, Notebook Power System
- Voltage - Input:
- 4.5V ~ 28V
- Number of Outputs:
- 4
- Voltage - Output:
- Adj to 1.2V
- Operating Temperature:
- -20°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 64-TQFP (10x10)
TPS5140PAG FAQ
1.How can I place an order for TPS5140PAG through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS5140PAG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS5140PAG reliable?
The price and inventory of TPS5140PAG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS5140PAG is usually 5 days.
3.What payment methods are accepted for TPS5140PAG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS5140PAG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS5140PAG?
TPS5140PAG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS5140PAG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS5140PAG?
For technical support, including TPS5140PAG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS5140PAG requirements.
6.How does Aetrix verify that TPS5140PAG is sourced from the original manufacturer or authorized distributors?
All TPS5140PAG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS5140PAG meets industry standards.
7.What is the process for return or replacement of TPS5140PAG?
All TPS5140PAG units undergo pre-shipment inspection (PSI). If there is an issue with TPS5140PAG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS5140PAG part is unused and in its original packaging.
Return procedure for TPS5140PAG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TPS5140PAG Tags
-
TPS51206DSQR
Texas Instruments
-
TPS51200DRCR
Texas Instruments
-
TPS51200DRCT
Texas Instruments
-
TPS62740DSSR
Texas Instruments
-
TPS51100DGQR
Texas Instruments
-
NCP51200MNTXG
onsemi
-
NCP51400MNTXG
onsemi
-
RT9026GSP
Richtek USA Inc.
-
LP2998MRX/NOPB
Texas Instruments
-
TPS51200QDRCRQ1
Texas Instruments
-
DPA423GN-TL
Power Integrations
-
LM10011SD/NOPB
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
