Texas Instruments TPS5140PAGRG4
- Part No.:
- TPS5140PAGRG4
- Manufacturer:
- Texas Instruments
- Category:
- Special Purpose Regulators
- Package:
- 64-TQFP
- Datasheet:
-
TPS5140PAGRG4.pdf
- Description:
- IC REG CTRLR NOTEBK 4OUT 64TQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TPS5140PAGRG4 from Texas Instruments is a quad-channel DC/DC controller IC integrating three synchronous-buck controllers (CH1–CH3) and one nonsynchronous 12-V boost converter, designed specifically for notebook PC peripheral power rails. It supports 4.5 V–28 V input, delivers adjustable step-down outputs down to 1.2 V, operates with PWM/SKIP mode auto-selection, and includes integrated 5-V and 3.3-V linear regulators - enabling compact, high-efficiency power management in space-constrained mobile platforms.
For engineers reviewing the TPS5140PAGRG4 datasheet, TPS5140PAGRG4 pinout, TPS5140PAGRG4 application, or TPS5140PAGRG4 equivalent, key selection considerations include per-channel standby control, programmable short-circuit protection via external TRIP resistors, independent soft-start timing per buck channel, and the dedicated 12-V boost output supporting PCMCIA power delivery at 120 mA.
Technical Context
The TPS5140PAGRG4 implements voltage-mode PWM control with independent error amplifiers per buck channel and a dedicated hysteresis-based skip comparator for light-load efficiency optimization. CH2 and CH3 operate in-phase while CH1 runs 180° out-of-phase to reduce input ripple and minimize required input capacitance.
Its 12-V boost converter integrates an N-channel PMOS switch and NMOS low-side driver (LL_UP), supports external Schottky diode configuration, and features separate OVP/UVP monitoring with SCP latching. The device also embeds dual linear regulators (5-V/50 mA and 3.3-V/30 mA), UVLO (4 V turn-on), and dead-time-controlled gate drivers to prevent shoot-through.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 4.5 V to 28 V - enables direct connection to wide-range battery or adapter inputs without pre-regulation. |
| Buck Output Voltage Range | Adjustable down to 1.2 V - supports core logic, memory, and I/O rail requirements across modern notebook SoCs. |
| Oscillator Frequency | 250 kHz typical (CT = 56 pF) - balances switching loss, EMI, and inductor size for portable applications. |
| Reference Voltage | 1.185 V ±1.5% - precision internal reference used for all feedback loops and protection thresholds. |
| Gate Drive Capability | OUT_u: ±1.2 A; OUT_d: ±1.5 A - sufficient to drive low-rDS(on) N-channel MOSFETs without external buffers. |
| Linear Regulators | VREF5: 5.0 V ±4%, 50 mA; VREF3.3: 3.3 V ±4.5%, 30 mA - powers internal circuitry and provides auxiliary system rails. |
| Protection Features | OVP/UVP on all channels (±7% PG, +12%/−18% OVP/UVP), programmable SCP delay, and per-channel STBY control - ensures robust fault response in multi-rail systems. |
Pinout & Package
The TPS5140PAGRG4 is housed in a 64-pin TQFP package (PAG) with exposed thermal pad, rated for −20°C to +85°C operation. Pin functions are validated per TI SLVS305A datasheet (Rev. January 2001).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| FB1/FB2/FB3 | Feedback input for CH1/CH2/CH3 | Connects to resistor divider to set output voltage; referenced to 1.185 V internal VREF. |
| LH1/LH2/LH3 | Bootstrap capacitor connection | Provides floating gate drive voltage for high-side N-MOSFETs; limits max LH-to-OUTGND = 33 V. |
| LL1/LL2/LL3 | Bootstrap return & current sense node | Connects to FET junction for floating drive and low-side RDS(on)-based current limiting. |
| OUT1_u/OUT2_u/OUT3_u | High-side gate drive output | ±1.2 A capable driver; requires external bootstrap capacitor for high-side FET turn-on. |
| OUT1_d/OUT2_d/OUT3_d | Low-side gate drive output | ±1.5 A capable driver; directly drives low-side N-MOSFET gates with 5-V swing from VREF5. |
| TRIP1/TRIP2/TRIP3 | Current limit programming input | External resistor sets overcurrent threshold via internal 13 µA current source (±10%). |
| STBY1/STBY2/STBY3 | Per-channel enable/disable control | Logic-level input (VIH = 2 V); grounding disables corresponding buck channel independently. |
| PG_DELAY | Power-good delay timer node | External capacitor sets delay before PGOUT assertion; internal current source = 1.7 µA typical. |
Key Features
| Feature | Design Value |
|---|---|
| Auto PWM/SKIP mode selection | PWM_SEL pin enables seamless transition between fixed-frequency PWM (heavy load) and burst-mode SKIP (light load), improving light-load efficiency without external control logic. |
| Phase-shifted buck operation | CH1 operates 180° out-of-phase with CH2/CH3, reducing input RMS current by ~30% and allowing smaller bulk input capacitors. |
| Integrated dual linear regulators | On-chip 5-V/50 mA and 3.3-V/30 mA LDOs eliminate need for external regulators, simplifying BOM and PCB layout for auxiliary bias rails. |
| Programmable short-circuit protection | SCP capacitor timing and TRIP-resistor current sensing allow precise tuning of fault response time and trip level per channel - critical for mixed-load notebook subsystems. |
| Dedicated 12-V boost converter | Includes internal PMOS switch and NMOS driver (LL_UP), supports 120 mA PCMCIA output, and features independent OVP/UVP with latch-off behavior. |
Applications
| Mobile CPU Core Power | Notebook I/O Rail Generation |
|---|---|
Use Scenario: Delivering tightly regulated 1.2–1.5 V to Intel Pentium M or AMD Mobile Athlon XP processor cores under dynamic load transients. IC Role / Device Role / Timing Role: Primary multi-phase buck controller managing CH1 (3.3 V) and CH2/CH3 (5 V / 2.5 V) with phase interleaving and independent soft-start sequencing. Use Value: Phase interleaving reduces input ripple by >40%, lowering required input capacitance and enabling thinner, lighter notebook designs. | Use Scenario: Generating stable 3.3 V and 5 V rails for USB controllers, card readers, and display interface ICs in clamshell-form-factor notebooks. IC Role / Device Role / Timing Role: Dual linear regulator (VREF3.3/VREF5) and synchronized buck outputs supply isolated, low-noise power with per-rail STBY control for selective subsystem shutdown. Use Value: Independent STBY1/STBY2/STBY3 pins allow OS-driven power gating of unused peripherals, extending battery life by >15% during idle states. |
| PCMCIA Slot Power Supply | Embedded Controller Biasing |
Use Scenario: Providing compliant 12 V ±5% at up to 120 mA to Type II PCMCIA cards (e.g., modems, LAN adapters) with hot-swap support. IC Role / Device Role / Timing Role: Nonsynchronous 12-V boost converter (CH4) with LL_UP/IN_12V/OUT_12V terminals and dedicated OVP/UVP comparators. Use Value: Integrated PMOS switch and NMOS driver eliminate external high-voltage FETs, reducing solution footprint by 35% vs discrete boost designs. | Use Scenario: Powering embedded keyboard controllers (KBC), EC firmware, and real-time clock circuits requiring ultra-low quiescent current during S3/S4 sleep states. IC Role / Device Role / Timing Role: Low-IQ shutdown mode (10 µA max) activated via STBY_VREF5/STBY_VREF3.3, with internal REF (1.185 V) remaining active for wake-up monitoring. Use Value: Sub-10 µA shutdown current extends battery hold-up time beyond 72 hours - meeting ACPI S5 "soft off" requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-channel notebook power controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS51100PAG | Single 3-phase buck controller (no boost or LDOs); 300 kHz max fosc; no integrated 12-V boost or linear regulators. | Suitable only for CPU core VRM; cannot replace TPS5140PAGRG4's multi-rail + PCMCIA + auxiliary LDO functionality. | Select when only high-current CPU core regulation is needed and auxiliary rails are handled externally. |
| RT8205AZSP | Triple buck + 12-V boost; lacks integrated 5-V/3.3-V LDOs; uses external reference; different pinout and protection thresholds. | Requires external 5-V bias for gate drivers; no VREF5/VREF3.3 outputs; PG logic and SCP timing differ significantly. | Choose only if redesigning full power tree and accepting added BOM cost for external regulators and reference. |
Compared with TPS5140PAGRG4, TPS51100PAG omits auxiliary rails and PCMCIA support entirely, while RT8205AZSP demands external biasing and offers no drop-in compatibility - making TPS5140PAGRG4 uniquely suited for legacy notebook platforms requiring integrated multi-rail, boost, and LDO functionality in one PAG-package IC.
Availability
TPS5140PAGRG4 is available at Aetrix Electronics and suitable for notebook PC motherboard design, mobile platform power architecture validation, and industrial embedded computing systems requiring stable component supply and long-lifecycle availability.
Supply support for TPS5140PAGRG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-reliability power conversion ICs.
The TPS5140 product line was engineered specifically for multi-rail notebook PC power architectures - integrating buck, boost, and linear regulation to replace discrete solutions and reduce system-level complexity in portable computing.
FAQ
What is the maximum operating frequency of the TPS5140PAGRG4 oscillator?
The TPS5140PAGRG4 oscillator operates at a typical frequency of 250 kHz in PWM mode with a 56-pF CT capacitor. The recommended maximum operating frequency is 300 kHz. This frequency is set by the external capacitor on the Ct pin and remains stable across temperature and input voltage variations, ensuring consistent switching behavior in notebook power applications.
Does the TPS5140PAGRG4 support independent soft-start for each buck channel?
Yes, the TPS5140PAGRG4 provides fully independent soft-start control via SOFTSTART1, SOFTSTART2, and SOFTSTART3 pins - each accepting an external capacitor to set individual ramp time. This allows staggered startup sequencing across CPU core, I/O, and memory rails, preventing inrush current overload and ensuring proper power-up order in complex notebook systems using the TPS5140PAGRG4.
How does the TPS5140PAGRG4 implement overvoltage and undervoltage protection?
The TPS5140PAGRG4 monitors INV1/INV2/INV3 inputs against its 1.185 V reference: OVP triggers at +12% (1.33 V) and UVP at −18% (0.97 V). Detection activates the SCP timer, which charges the external SCP capacitor. After a programmable delay, all affected channel drivers latch off. This dual-threshold scheme is applied identically to the 12-V boost output with dedicated thresholds (12.9 V OVP, 9.5 V UVP), ensuring reliable rail integrity for the TPS5140PAGRG4.
Can the TPS5140PAGRG4 operate with an external 5-V supply instead of its internal regulator?
Yes - when a valid 4.2–5.5 V supply is applied to REG5V_IN, the TPS5140PAGRG4 automatically disables its internal 5-V linear regulator and routes the external 5 V to both high-side bootstrap circuits and low-side drivers. This improves overall efficiency by eliminating LDO dropout losses and is confirmed in the functional description and Logic Chart 2 of the TPS5140PAGRG4 datasheet.
What is the purpose of the PHASE_12V pin on the TPS5140PAGRG4?
The PHASE_12V pin is provided for optional phase compensation of the 12-V boost converter loop. However, the datasheet explicitly states it is "not typically connected" and that the boost converter is stable without external compensation. Leaving PHASE_12V open is the default, validated configuration for the TPS5140PAGRG4 - adding external components is only necessary if specific stability issues arise under unusual load or layout conditions.
TPS5140PAGRG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 64-TQFP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Applications:
- Controller, Notebook Power System
- Voltage - Input:
- 4.5V ~ 28V
- Number of Outputs:
- 4
- Voltage - Output:
- Adj to 1.2V
- Operating Temperature:
- -20°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 64-TQFP (10x10)
TPS5140PAGRG4 FAQ
1.How can I place an order for TPS5140PAGRG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS5140PAGRG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS5140PAGRG4 reliable?
The price and inventory of TPS5140PAGRG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS5140PAGRG4 is usually 5 days.
3.What payment methods are accepted for TPS5140PAGRG4?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS5140PAGRG4 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS5140PAGRG4?
TPS5140PAGRG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS5140PAGRG4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS5140PAGRG4?
For technical support, including TPS5140PAGRG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS5140PAGRG4 requirements.
6.How does Aetrix verify that TPS5140PAGRG4 is sourced from the original manufacturer or authorized distributors?
All TPS5140PAGRG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS5140PAGRG4 meets industry standards.
7.What is the process for return or replacement of TPS5140PAGRG4?
All TPS5140PAGRG4 units undergo pre-shipment inspection (PSI). If there is an issue with TPS5140PAGRG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS5140PAGRG4 part is unused and in its original packaging.
Return procedure for TPS5140PAGRG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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