Texas Instruments TPS51461RGER
- Part No.:
- TPS51461RGER
- Manufacturer:
- Texas Instruments
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
TPS51461RGER.pdf
- Description:
- IC REG BUCK PROG 6A 24VQFN
- Quantity:
- Payment:

- Shipping:

Inventory:193
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TPS51461RGER from Texas Instruments is a fully integrated synchronous step-down DC-DC converter with D-CAP+™ adaptive on-time control, 2-bit VID interface, and integrated high-side/low-side FETs. It delivers up to 6-A output current from 3.3-V or 5-V input rails, supports Intel System Agent (SA) voltage regulation with ±1.5% VOUT accuracy at 0.675–0.9 V, and operates in 700 kHz or 1 MHz switching frequencies. It is used in notebook/desktop CPU power delivery for system agent rail regulation.
For engineers reviewing the TPS51461RGER datasheet, TPS51461RGER pinout, TPS51461RGER application, or TPS51461RGER equivalent, key selection considerations include its 24-pin QFN package, VID-programmable output voltage, droop/non-droop configuration capability via COMP–VREF network, integrated 5-V gate driver supply (V5DRV/V5FILT), and thermal shutdown at 130°C with 10°C hysteresis.
Technical Context
The TPS51461RGER implements D-CAP+™ mode using current-sense amplifier feedback (ACSINT = 53 mV/A nominal) combined with VOUT differential sensing to improve transient response and reduce layout sensitivity. Its adaptive on-time generator adjusts tON based on VIN, VOUT, and current feedback to maintain stable frequency under load and line variation.
It supports two distinct compensation modes: non-droop (flat load regulation via type-II RC network between COMP and VREF) and droop (voltage positioning via RDROOP resistor to achieve target load-line slope, e.g., 5 mΩ). VID transitions are slew-rate controlled by external capacitor on SLEW pin (10 µA current source), enabling precise voltage ramping per Intel platform timing requirements.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Current | 6 A maximum continuous - supports full Intel SA rail load without external current sharing |
| Input Voltage Range | 3.3 V to 6.5 V - compatible with standard 3.3-V and 5-V system rails |
| Output Voltage Range | 0.675 V to 0.9 V (VID-selectable) - matches Intel SA voltage codes for SV/LV/ULV processors |
| VOUT Accuracy | ±1.5% at 0.8 V - ensures compliance with Intel SA DC tolerance spec |
| Switching Frequency | Selectable 700 kHz or 1 MHz - enables trade-off between size (inductor/capacitor) and efficiency |
| Thermal Shutdown | 130°C with 10°C hysteresis - protects against sustained overload or poor PCB thermal design |
| PGOOD Threshold | 84%–86% (assert), 114%–118% (de-assert) of VSLEW - provides tight power-good window for system sequencing |
Pinout & Package
TPS51461RGER is housed in a 4 mm × 4 mm, 24-pin thermally enhanced QFN package (RGE) with exposed thermal pad. Pin 24 is the thermal pad, electrically connected to PGND.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN (Pins 3, 5, 21–23) | Power input | Drain connection of high-side FET; accepts 3.3-V/5-V rail; multiple pins reduce IR drop and improve thermal path |
| SW (Pins 7–11) | Switching node | Source of high-side FET / drain of low-side FET; connects to inductor; used for current sensing and bootstrap charging |
| PGND (Pins 19–20, 22–23) | Power ground | Source of low-side FET; primary return path for high-current switching loop; critical for EMI and stability |
| BST (Pin 12) | Bootstrap supply | Connects 0.1-µF ceramic capacitor to SW; powers high-side gate driver; enables 100% duty cycle capability |
| V5DRV / V5FILT (Pins 18, 17) | 5-V analog/driver supply | Dedicated 5-V supplies for gate driver (V5DRV) and analog circuitry (V5FILT); each has independent UVLO (4.3 V) |
| VID0 / VID1 (Pins 14–15) | 2-bit VID input | Set output voltage per Intel SA table (e.g., 0.675 V, 0.725 V, 0.80 V, 0.85 V); pull-down resistors required |
| SLEW (Pin 4) | Voltage transition control | 10-µA current source charges external capacitor to program startup/voltage-transition slew rate (e.g., 1 mV/µs) |
| COMP (Pin 3) | Loop compensation | Connects RC network to VREF for type-II compensation; determines stability and transient response in non-droop mode |
Key Features
| Feature | Design Value |
|---|---|
| D-CAP+™ adaptive on-time control | Combines current-sense feedback (53 mV/A) and VOUT differential sensing to minimize output capacitance and improve transient response without external compensation |
| Integrated 2-bit VID interface | Direct support for Intel SA voltage codes (0.675–0.9 V) with on-the-fly transitions and programmable slew rate via SLEW pin |
| Droop and non-droop configuration | Selectable via COMP–VREF resistor network: non-droop for flat load regulation; droop for voltage positioning (e.g., 5-mΩ load line) |
| Auto-skip mode at light load | Discontinuous conduction mode (DCM) activation reduces switching losses and improves efficiency below ~1 A |
| Comprehensive protection suite | Includes OVP (120% VSLEW), UVP (70% VSLEW), overcurrent (±6 A valley limit), thermal shutdown (130°C), and 5-V UVLO (4.3 V) |
Applications
| Intel System Agent Power Rail | Notebook CPU Core Voltage Sequencing |
|---|---|
Use Scenario: Regulating VCCSA rail for 2nd–4th gen Intel Core processors in ultrabook platforms with strict space constraints and dynamic VID transitions. IC Role / Device Role / Timing Role: Primary synchronous buck controller with integrated FETs, VID decoding, and slew-controlled voltage transitions per Intel platform timing diagrams (e.g., 2.5-ms VID toggle window). Use Value: Eliminates need for external MOSFETs and VID DAC; achieves ±1.5% VOUT accuracy and <4% transient deviation with only four 22-µF MLCCs. |
Use Scenario: Providing tightly regulated, sequenced power to CPU uncore domains during boot and performance state (P-state) transitions. IC Role / Device Role / Timing Role: Dual-rail controller supporting both fixed-VID startup and dynamic VID updates; PGOOD signal synchronized to processor reset timing (900-ms window). Use Value: Enables single-chip solution for VCCSA and VCCIO auxiliary rails; reduces BOM count by 7 components versus discrete controller + FET design. |
| Desktop Platform SA Voltage Regulation | Low-Power Embedded x86 SoC Supply |
Use Scenario: Delivering 6-A peak current to desktop motherboard SA rail with high efficiency across 0.01–6 A load range. IC Role / Device Role / Timing Role: High-current buck regulator with selectable 700 kHz/1 MHz frequency; thermal pad enables >2 W dissipation on 2-layer PCB. Use Value: Achieves >85% efficiency at 1 A (VIN = 5 V) and >90% at 3 A via auto-skip mode and low RDS(on) FETs (typ. 12 mΩ HS / 7 mΩ LS). |
Use Scenario: Powering fanless embedded systems with x86 SoCs requiring low-noise, low-acoustic operation and extended temperature support. IC Role / Device Role / Timing Role: Compact 4×4 mm regulator with -40°C to 85°C rating; soft-start slew rate limits inrush current and prevents audible coil whine. Use Value: Enables silent operation via programmable 0.5–10 mV/µs slew rate; eliminates need for external soft-start IC or complex sequencing logic. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS51462RGER | Same pinout and VID interface; adds VIN UVLO (2.5 V min) and improved light-load efficiency via enhanced auto-skip algorithm | Preferred for new designs requiring wider input range or lower standby power; not drop-in due to different EN threshold (0.4 V vs 0.8 V) | Select TPS51462RGER when designing for 2.5–5.5 V input or targeting <50 µA quiescent current |
| ISL95831IRZ | 3-phase controller with external FETs; supports up to 25 A; no integrated VID decoder; requires external DAC and sequencing logic | Used in high-performance desktop/server SA rails where >6 A is needed; lacks integrated 5-V supplies and SLEW control | Choose ISL95831IRZ only when scaling beyond 6 A or requiring multi-phase interleaving for ripple reduction |
Compared with TPS51461RGER, TPS51462RGER offers tighter input UVLO and lower IQ but requires firmware-level EN logic adjustment, while ISL95831IRZ provides higher current headroom at the cost of increased board area, component count, and design complexity.
Availability
TPS51461RGER is available at Aetrix Electronics and suitable for notebook motherboard design, Intel platform SA power delivery, and embedded x86 SoC applications requiring stable component supply, long-lifecycle availability, and RoHS-compliant packaging.
Supply support for TPS51461RGER includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in power conversion architecture and Intel platform reference designs.
The TPS51461RGER belongs to TI's D-CAP+™ synchronous buck converter product line, designed specifically for Intel system agent and CPU core voltage regulation with integrated VID, thermal robustness, and minimal external component count.
FAQ
What is the recommended output capacitor configuration for TPS51461RGER in non-droop mode?
The TPS51461RGER supports all-MLCC output capacitor configurations in non-droop mode. For Intel SA applications, TI recommends four 22-µF, X5R, 6.3-V ceramic capacitors (e.g., Murata GRM21BR60J226ME39L) placed close to the IC. This configuration achieves <1% output ripple and meets Intel's 0.8-V ±5% transient window requirement without requiring POSCAP or polymer capacitors.
How does the SLEW pin control voltage transitions in TPS51461RGER?
The SLEW pin on the TPS51461RGER hosts a 10-µA internal current source that charges an external capacitor (e.g., 10 nF) to set the output voltage slew rate. For example, a 10-nF capacitor yields ~1 mV/µs slew rate, ensuring VID transitions (e.g., 0.9 V → 0.8 V) complete within Intel's 2.5-ms timing window while minimizing inductor current perturbation and acoustic noise.
Can TPS51461RGER operate with a 3.3-V input supply?
Yes, the TPS51461RGER supports 3.3-V input operation across its full –40°C to 85°C ambient range. At VIN = 3.3 V, it maintains 6-A output capability and >85% efficiency at 3-A load (Mode 3, fSW = 700 kHz). The 5-V gate driver supplies (V5DRV/V5FILT) are internally generated from VIN, eliminating need for external 5-V rail.
What is the function of the MODE pin on TPS51461RGER?
The MODE pin on the TPS51461RGER selects switching frequency (700 kHz or 1 MHz) and VREF voltage (2.01 V or 2.06 V) by connecting to GND, 22 kΩ, 33 kΩ, 47 kΩ, 100 kΩ, or left open. Each setting corresponds to a specific VID code and compensation mode (e.g., MODE = 33 kΩ selects 700 kHz and 0.80 V output for LV processors). Table 3 in the datasheet defines all eight valid configurations.
Does TPS51461RGER require external bootstrap diode or capacitor?
No, the TPS51461RGER integrates a bootstrap switch and requires only a 0.1-µF ceramic capacitor between BST and SW pins. The internal BST switch (RDS(on) = 5–10 Ω) eliminates need for external diode, reducing component count and PCB area. TI recommends X7R or X5R dielectric for stable capacitance across temperature and bias.
TPS51461RGER Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- D-CAP+™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Programmable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 3.3V
- Voltage - Input (Max):
- 5V
- Voltage - Output (Min/Fixed):
- 0.675V, 0.725V, 0.8V, 0.85V, 0.9V
- Voltage - Output (Max):
- -
- Current - Output:
- 6A
- Frequency - Switching:
- 700kHz, 1MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-VQFN (4x4)
TPS51461RGER FAQ
1.How can I place an order for TPS51461RGER through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS51461RGER on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS51461RGER reliable?
The price and inventory of TPS51461RGER are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS51461RGER is usually 5 days.
3.What payment methods are accepted for TPS51461RGER?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS51461RGER transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS51461RGER?
TPS51461RGER orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS51461RGER order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS51461RGER?
For technical support, including TPS51461RGER datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS51461RGER requirements.
6.How does Aetrix verify that TPS51461RGER is sourced from the original manufacturer or authorized distributors?
All TPS51461RGER products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS51461RGER meets industry standards.
7.What is the process for return or replacement of TPS51461RGER?
All TPS51461RGER units undergo pre-shipment inspection (PSI). If there is an issue with TPS51461RGER, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS51461RGER part is unused and in its original packaging.
Return procedure for TPS51461RGER:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TPS51461RGER Tags

-
TPS562201DDCR
Texas Instruments

-
MC34063ABD-TR
STMicroelectronics

-
TPS561201DDCR
Texas Instruments

-
MC33063ADR
Texas Instruments

-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments

-
AP3012KTR-G1
Diodes Incorporated

-
TLV61048DBVR
Texas Instruments

-
AZ34063UMTR-G1
Diodes Incorporated

-
TPS562200DDCR
Texas Instruments

-
AP62300TWU-7
Diodes Incorporated

-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

