Texas Instruments TPS51461RGET

Overview

TPS51461RGET from Texas Instruments is a fully integrated synchronous step-down DC-DC converter with D-CAP+™ adaptive on-time control, 2-bit VID interface, and integrated high-side/low-side FETs. It delivers up to 6-A output current from 3.3-V or 5-V input rails, supports Intel System Agent (SA) voltage regulation with ±1.5% VOUT accuracy at 0.675–0.9 V, and operates in 700 kHz or 1 MHz switching frequencies. It is used in notebook/desktop CPU power delivery for system agent rail regulation.

For engineers reviewing the TPS51461RGET datasheet, TPS51461RGET pinout, TPS51461RGET application, or TPS51461RGET equivalent, key selection criteria include VID-programmable output voltage (0.675 V to 0.9 V), integrated FETs enabling minimal external component count, droop/non-droop configuration flexibility via COMP–VREF network, 10-µA SLEW pin current source for precise voltage transition timing, and thermal shutdown at 130°C with 10°C hysteresis.

Technical Context

The TPS51461RGET implements D-CAP+™ mode using adaptive on-time control where PWM cycle initiation depends on current feedback (VCS) crossing the error amplifier output (VCOMP), not fixed reference crossing. Its 2-bit VID inputs select one of four output voltages (0.675 V, 0.725 V, 0.80 V, or 0.85 V) with MODE pin biasing determining frequency (700 kHz or 1 MHz) and reference voltage (2.01 V or 2.06 V).

It supports both droop (voltage positioning) and non-droop configurations: droop uses a resistor between COMP and VREF to set load-line slope (e.g., 10 kΩ for 5-mΩ droop), while non-droop employs type-II compensation for flat load regulation. The SLEW pin controls startup and VID-transition slew rate via external capacitor and internal 10-µA current source, independent of switching frequency or output loading.

Key Specifications

Pinout & Package

TPS51461RGET is housed in a 4 mm × 4 mm, 24-pin QFN package (RGE) with exposed thermal pad. Pin numbering follows standard counter-clockwise layout starting from top-left corner (Pin 1 = GND). Package is RoHS-compliant and lead-free.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous buck converter applications.

Compared with TPS51461RGET, TPS51462RGET adds VCCIO capability at the expense of higher cost and complexity, while ISL95831IRZ-T lacks integrated VID and slew control - making TPS51461RGET the optimal choice for cost-sensitive, space-constrained Intel SA rail applications requiring precise voltage transitions.

Availability

TPS51461RGET is available at Aetrix Electronics and suitable for notebook motherboard design, Intel platform power delivery, and embedded controller supply applications requiring stable component supply, consistent parametric performance, and long-term lifecycle support.

Supply support for TPS51461RGET includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with over 50 years of innovation in power conversion ICs.

The TPS51461RGET belongs to TI's D-CAP+™ synchronous buck converter product line, designed specifically for Intel CPU system agent and core voltage regulation with emphasis on VID compatibility, minimal external components, and thermal robustness in space-constrained mobile platforms.

FAQ

What is the maximum output current capability of the TPS51461RGET?

The TPS51461RGET supports a maximum continuous output current of 6 A using its integrated high-side and low-side MOSFETs. This rating is validated across the full operating temperature range (–40°C to 85°C) with proper PCB thermal design, including use of the exposed thermal pad. Peak current capability remains stable due to valley-current limiting with a minimum trip point of 6 A, ensuring reliable operation under transient load steps.

How does the TPS51461RGET implement VID-on-the-fly voltage transitions?

The TPS51461RGET implements VID-on-the-fly transitions using its dedicated SLEW pin, which sources a precise 10-µA current to charge an external capacitor. This generates a controlled ramp on the internal reference, allowing smooth output voltage slewing (e.g., from 0.9 V to 0.8 V) without overshoot. During transition, the device enters forced PWM mode for 64 µs post-slew to ensure regulation stability - a feature critical for Intel processor C-state compliance.

Can the TPS51461RGET operate with only ceramic output capacitors?

Yes, the TPS51461RGET is explicitly designed to work with all-MLCC output capacitors, enabled by its D-CAP+™ control architecture. Unlike conventional voltage-mode controllers, it does not require ESR-based zero compensation - eliminating dependency on POSCAP or polymer capacitors. Reference designs confirm stable operation with 4×22 µF X5R ceramics, reducing solution size and improving reliability versus electrolytic alternatives.

What protection features are integrated into the TPS51461RGET?

The TPS51461RGET integrates comprehensive protection: 5-V UVLO (4.3 V trip with 440 mV hysteresis), output OVP (120% of VSLEW), UVP (70% of VSLEW with 8-µs delay), cycle-by-cycle valley overcurrent limiting (±6 A), and thermal shutdown at 130°C with 10°C hysteresis. All protections latch off the controller until reset via EN toggle or 5-V POR - preventing uncontrolled restarts during fault conditions.

What is the purpose of the MODE pin on the TPS51461RGET?

The MODE pin on the TPS51461RGET selects both switching frequency (700 kHz or 1 MHz) and internal reference voltage (2.01 V or 2.06 V) via resistor pull-down values (e.g., 33 kΩ for 700 kHz/2.01 V, 100 kΩ for 700 kHz/2.01 V). This dual function enables optimization of efficiency vs. size trade-offs: 1 MHz allows smaller inductors, while 700 kHz improves light-load efficiency and EMI filter design margin.