Texas Instruments TPS51640ARSLR

Overview

TPS51640ARSLR from Texas Instruments is a dual-output, high-efficiency synchronous buck controller IC designed exclusively for IMVP-7/8 mobile CPU core and I/O power delivery under Intel's confidential disclosure agreement. It supports 1–2-phase operation per rail, delivers up to 200 A total output current, operates from 4.5–24 V input, and features adaptive on-time D-CAP2 control with ±0.5% VOUT accuracy at 0.5–1.5 V output range-used in ultrabook and thin-and-light laptop VRMs.

For engineers reviewing the TPS51640ARSLR datasheet, TPS51640ARSLR pinout, TPS51640ARSLR application, or TPS51640ARSLR equivalent, key selection criteria include IMVP compliance, dual-rail phase interleaving capability, integrated MOSFET driver support, thermal performance in 6×6 mm VQFN-48, and Intel CNDA requirement verification prior to design-in.

Technical Context

The TPS51640ARSLR implements two independent D-CAP2-controlled buck controllers-one for CPU core (VCC) and one for CPU I/O (VCCIO)-with programmable phase count (1–2 per rail), adaptive dead-time control, and seamless transition between pulse-width modulation (PWM) and pulse-frequency modulation (PFM) modes. It integrates gate drivers capable of driving external high-side and low-side N-channel MOSFETs with 1.5-A sink/source peak current.

It supports Intel VRReady™ compliance via SVID interface (4-wire serial voltage identification bus), real-time telemetry reporting (temperature, current, voltage), and dynamic VID updates. The device operates across –10°C to +105°C ambient and requires external compensation networks for stability across varying load and output capacitor ESR conditions.

Key Specifications

Pinout & Package

VQFN-48 (RSL) package with wettable flanks, exposed thermal pad, and 0.4 mm pitch. Pin 1 located in Quadrant Q2 per tape orientation standard. Package height ≤1 mm enables low-profile VRM designs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-rail IMVP-compliant buck controller applications.

Compared with TPS51640ARSLR, TPS59640RSLR extends cold-temperature operation but lacks VRHot support, while TPS59641RSLR adds VRHot and higher-resolution telemetry-both retain identical layout, SVID timing, and phase control architecture for drop-in compatibility in most IMVP-7/8 designs.

Availability

TPS51640ARSLR is available at Aetrix Electronics and suitable for ultrabook VRM design, thin-and-light laptop power systems, and Intel mobile processor reference platforms requiring stable component supply and long-term lifecycle support.

Supply support for TPS51640ARSLR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, specializing in analog, embedded processing, and power management technologies with over 90 years of innovation history.

The TPS516xx family was developed specifically to meet Intel's IMVP-7/8 specification for mobile CPU voltage regulator modules, emphasizing SVID compliance, dual-rail independence, and high-current transient response in compact form factors.

FAQ

Is TPS51640ARSLR compatible with Intel 11th-generation Core mobile processors?

No, TPS51640ARSLR is specified for IMVP-7/8 platforms (e.g., 4th–10th gen Intel Core mobile). For 11th-gen and later, Intel requires VRHot support and enhanced telemetry-functions added in TPS59641RSLR. Using TPS51640ARSLR on 11th-gen+ CPUs may result in boot failure or thermal protection errors. Always verify platform-specific VRM requirements before selecting TPS51640ARSLR.

Does TPS51640ARSLR require an Intel CNDA to use in production?

Yes, TPS51640ARSLR is governed by Intel's Confidential Disclosure Agreement (CNDA) for IMVP technology. End users must have an active CNDA with Intel before designing in or purchasing TPS51640ARSLR. TI enforces this restriction-no exceptions are granted. Contact [email protected] to initiate CNDA onboarding before engaging with TPS51640ARSLR.

What is the maximum supported output current for each rail on TPS51640ARSLR?

TPS51640ARSLR does not define fixed current limits-it supports scalable output current based on external MOSFET selection, PCB layout, and thermal design. Typical implementations deliver up to 150 A on VCC (core) and 50 A on VCCIO (I/O) using 2-phase and 1-phase configurations respectively. Peak current capability depends on MOSFET RDS(on), inductor saturation rating, and thermal management of the TPS51640ARSLR's 6×6 mm VQFN package.

Can TPS51640ARSLR operate without SVID communication?

No, TPS51640ARSLR requires active SVID communication for initialization and regulation. It lacks internal default VID settings and will not generate valid output voltages without SVID clock and data signals from the CPU or EC. If SVID is disconnected or inactive, both PGOOD outputs remain deasserted and the device stays in reset-TPS51640ARSLR cannot be used in non-SVID or fixed-VOUT applications.

What package variant is used for TPS51640ARSLR, and is it RoHS compliant?

TPS51640ARSLR uses the VQFN-48 (RSL) package: 6 mm × 6 mm, 0.4 mm pitch, 1 mm max height, with wettable flanks and exposed thermal pad. It is fully RoHS compliant (lead-free, NIPDAU finish) and rated MSL Level-1 (unlimited floor life at ≤30°C/60% RH). The part marking "TPS51640A" appears on the top surface, and reel packaging follows TI's standard 2500-unit large tape-and-reel format.