Texas Instruments TPS51640RSLR
- Part No.:
- TPS51640RSLR
- Manufacturer:
- Texas Instruments
- Category:
- Microcontrollers
- Package:
- -
- Datasheet:
-
TPS51640RSLR.pdf
- Description:
- 2+1 IMVP7 CPU CONTROLLER
- Quantity:
- Payment:

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Inventory:290,000
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Product details
Overview
TPS51640RSLR from Texas Instruments is a dual-channel IMVP-7-compliant step-down controller integrating two gate drivers for 3-phase CPU and 1-phase GPU power delivery. It supports SVID interface, D-CAP+™ control architecture, 8-bit DAC (0.250–1.52 V), VCORE overshoot/undershoot reduction (OSR/USR), and operates from –10°C to 105°C in a 48-pin QFN package. It targets high-performance laptop and ultrabook processor voltage regulation.
For engineers reviewing the TPS51640RSLR datasheet, TPS51640RSLR pinout, TPS51640RSLR application, or TPS51640RSLR equivalent, key selection criteria include IMVP-7 SVID compliance, integrated dual FET drivers, phase-balancing capability, adjustable slew rate via SLEWA, and support for both adapter/battery input rails (3–28 V).
Technical Context
The TPS51640RSLR implements D-CAP+™ control with overlapping pulse support for undershoot reduction (USR) and dedicated OSR circuitry, enabling fast transient response with minimal output capacitance. Its dual-channel architecture separates CPU and GPU regulation paths, each with independent frequency selection (8 options per channel), current limit configuration, and thermal monitoring via CTHERM/GTHERM pins.
It integrates two high-speed N-channel FET drivers (CDH1/CDL1, CDH2/CDL2) for CPU phases 1 and 2, while relying on an external driver (e.g., TPS51601) for CPU phase 3 and GPU channel. The controller supports light-load single-phase operation and full IMVP-7 I/O including dual PGOOD, ALERT, VR_HOT, and digital current monitor outputs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Topology | Dual-channel synchronous buck controller: 3-phase CPU + 1-phase GPU |
| SVID Compliance | Fully compliant with Intel IMVP-7 specification for serial VID communication and VR enable/control |
| Output Voltage Range | 0.250 V to 1.52 V via 8-bit DAC; supports dynamic VID scaling during operation |
| Input Voltage Range | 3 V to 28 V - accommodates adapter, battery, NVDC, and 3/5/12 V rail inputs |
| Operating Temperature | –10°C to 105°C - rated for mobile platform thermal environments |
| Package | 48-pin QFN (6 mm × 6 mm), PowerPAD™ thermally enhanced package |
| Driver Integration | Two integrated high-current FET drivers for CPU phases 1 & 2; third CPU phase and GPU require external driver (e.g., TPS51601) |
Pinout & Package
TPS51640RSLR is housed in a thermally optimized 48-pin QFN (RSL) package with exposed PowerPAD™ for enhanced heat dissipation. Pin functions are fully defined per TI SLUSAQ2 datasheet, with dedicated signal groups for CPU/GPU sensing, drive, thermal, and SVID interface.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CDH1 / CDL1 | CPU Phase 1 gate drive outputs | High-side and low-side N-FET drive signals with <2.5 Ω ON resistance and <40 ns transition time |
| CDH2 / CDL2 | CPU Phase 2 gate drive outputs | Independent drive outputs supporting interleaved 3-phase operation with AutoBalance™ phase balancing |
| CPWM3 / CSKIP | CPU Phase 3 control outputs | 5-V logic-level PWM and skip-mode signals for external driver (e.g., TPS51601) controlling third CPU phase |
| GPWM / GSKIP | GPU channel control outputs | 5-V logic-level PWM and skip-mode signals for external GPU driver |
| CVFB / GVFB | CPU/GPU voltage feedback inputs | Direct connection to VCORE/VGFX; includes integrated soft-stop transistor for controlled shutdown |
| CCSP1–3 / CCSN1–3 | CPU current sense inputs | Positive/negative inputs for DCR or resistor-based current sensing per phase; CCSPx tie-to-V3R3 disables phase |
| GCSP / GCSN | GPU current sense inputs | Single-phase GPU current sensing with secondary OVP comparator on GCSN |
| SLEWA | Slew rate configuration input | Analog voltage (0–2.5 V) sets VCORE slew rate from 1.25 to 26 mV/µs; latched at startup |
Key Features
| Feature | Design Value |
|---|---|
| D-CAP+™ Control Architecture | Enables ultra-fast transient response without external compensation; reduces required output capacitance by up to 50% vs. conventional voltage-mode controllers |
| VCORE Overshoot/Undershoot Reduction | Configurable OSR/USR thresholds (via RxSKIP resistors) actively suppress voltage excursions during load transients - critical for IMVP-7 compliance |
| AutoBalance™ Phase Balancing | Patent-pending internal current sharing ensures ≤±3% imbalance across CPU phases under steady-state and transient conditions |
| Dual Independent Frequency Selection | 8 selectable switching frequencies per channel (250–660 kHz CPU; 275–660 kHz GPU) via RCF/RGF resistors - enables optimization of efficiency vs. size |
| Integrated Digital Current Monitor | Analog current monitor outputs (CIMON/GIMON) provide real-time load current with ±1% accuracy over temperature for system telemetry and protection |
Applications
| Ultra-Thin Laptop CPU Regulation | Gaming Notebook GPU Power Delivery |
|---|---|
Use Scenario: Regulating VCORE for Intel Core i7/i9 processors in sub-15mm clamshell designs with dual-input (adapter + battery) power architecture. IC Role / Device Role / Timing Role: Primary IMVP-7 VCORE controller managing 3-phase CPU buck conversion, SVID command execution, and thermal throttling coordination. Use Value: Enables <1.5% voltage deviation during 66-A load steps (VIN=9 V), meeting IMVP-7 transient spec while reducing bulk capacitor count by 30%. | Use Scenario: Delivering stable VGFX to discrete NVIDIA GeForce RTX GPUs in 17-inch gaming notebooks with independent thermal zones. IC Role / Device Role / Timing Role: Dedicated 1-phase GPU buck controller with synchronized soft-start/soft-stop and VR_HOT signaling to GPU die. Use Value: Provides 92% peak efficiency at 50 A (VIN=19.5 V), with <50 µs VR_ON-to-PGOOD delay ensuring GPU boot sequencing integrity. |
| Mobile Workstation Dual-VR System | Convertible Tablet Processor Platform |
Use Scenario: Simultaneous regulation of high-power CPU and GPU in mobile workstations requiring sustained all-core turbo and GPU compute loads. IC Role / Device Role / Timing Role: Dual-channel controller coordinating CPU/GPU power states via shared SVID bus and independent PGOOD/ALERT signaling. Use Value: Supports PS0–PS3 power state transitions with <100 µs VID update latency and coordinated slew-rate control to prevent cross-rail coupling. | Use Scenario: Power management in 2-in-1 detachable tablets where CPU must operate reliably across battery-only (7.4 V) and docked (19.5 V) input conditions. IC Role / Device Role / Timing Role: Adaptive buck controller with wide 3–28 V input range and automatic light-load single-phase mode to extend battery life. Use Value: Maintains >85% efficiency at 1-A load (PS3 state) and <10 µA V5DRV standby current, extending runtime by 18 minutes per charge cycle. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel IMVP-7 controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS59640RSLR | Wider operating temperature (–40°C to 105°C); VBOOT = 0 V; identical pinout and feature set | Required for industrial or extended-temperature laptop designs; same PCB layout and firmware | Select when ambient operating temperature may fall below –10°C |
| TPS59641RSLR | VBOOT = 1.1 V (vs. 0 V); otherwise identical electrical specs, pinout, and IMVP-7 functionality | Designed for systems using DrMOS with 1.1-V bootstrap supply; requires matching external driver | Select only when paired with 1.1-V bootstrap DrMOS (e.g., TPS53689) |
Compared with TPS51640RSLR, TPS59640RSLR extends cold-temperature operation without layout change, while TPS59641RSLR enables tighter integration with 1.1-V DrMOS but mandates VBOOT-compatible external drivers - neither is drop-in; both require validation of thermal and bootstrap supply design.
Availability
TPS51640RSLR is available at Aetrix Electronics and suitable for ultra-thin laptop CPU regulation, gaming notebook GPU power delivery, and mobile workstation dual-VR systems requiring stable component supply across long production lifecycles.
Supply support for TPS51640RSLR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs for industrial, automotive, and computing applications.
The TPS516xx family delivers IMVP-7-compliant multi-phase VR solutions targeting high-efficiency, low-noise, and thermally constrained mobile computing platforms - designed specifically for Intel processor voltage regulation requirements.
FAQ
What is the maximum supported CPU phase count for TPS51640RSLR?
The TPS51640RSLR natively controls three CPU phases: two phases (Phase 1 and Phase 2) via integrated drivers (CDH1/CDL1, CDH2/CDL2), and the third phase (Phase 3) via external PWM/SKIP signals (CPWM3/CSKIP) driving an external driver such as TPS51601. This architecture enables full 3-phase CPU operation with balanced current sharing.
Does TPS51640RSLR support both CPU and GPU voltage regulation simultaneously?
Yes, TPS51640RSLR is a dual-channel controller: its CPU channel supports 1-, 2-, or 3-phase operation for VCORE, while its independent GPU channel provides dedicated 1-phase regulation for VGFX. Both channels share SVID interface but maintain separate feedback, current sensing, thermal monitoring, and PGOOD outputs - enabling true concurrent regulation.
What is the function of the SLEWA pin on TPS51640RSLR?
The SLEWA pin on TPS51640RSLR sets the VCORE voltage slew rate during startup, shutdown, and dynamic VID transitions. Applying 0.4–2.5 V selects a linearly scalable slew rate from 3.5 to 26 mV/µs; the value is latched at VR_ON assertion. This enables precise control of inrush current and meets IMVP-7 voltage positioning requirements across power states.
Can TPS51640RSLR operate with a 12-V input rail?
Yes, TPS51640RSLR supports input voltages from 3 V to 28 V, making it fully compatible with standard 12-V adapter rails. Electrical characteristics (e.g., tTON_CPU, efficiency curves, thermal performance) are validated at 12 V in the datasheet, and typical applications use 12-V input for CPU/GPU VRMs in mainstream laptops and workstations.
How does TPS51640RSLR implement IMVP-7 thermal protection?
TPS51640RSLR implements IMVP-7 thermal protection via CTHERM and GTHERM pins, each forming a resistor-thermistor divider referenced to VREF. The controller monitors resulting voltage levels and asserts VR_HOT (active-low) when thermal register bits indicate die temperature exceeds programmed thresholds (e.g., 783 mV = 75°C). Deglitching ensures robust noise immunity with 1-ms sampling.
TPS51640RSLR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- -
- Series:
- *
- Packaging:
- Bulk
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- -
- Core Size:
- -
- Speed:
- -
- Connectivity:
- -
- Peripherals:
- -
- Number of I/O:
- -
- Program Memory Size:
- -
- Program Memory Type:
- -
- EEPROM Size:
- -
- RAM Size:
- -
- Voltage - Supply (Vcc/Vdd):
- -
- Data Converters:
- -
- Oscillator Type:
- -
- Operating Temperature:
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- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
TPS51640RSLR FAQ
1.How can I place an order for TPS51640RSLR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS51640RSLR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS51640RSLR reliable?
The price and inventory of TPS51640RSLR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS51640RSLR is usually 5 days.
3.What payment methods are accepted for TPS51640RSLR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS51640RSLR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS51640RSLR?
TPS51640RSLR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS51640RSLR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS51640RSLR?
For technical support, including TPS51640RSLR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS51640RSLR requirements.
6.How does Aetrix verify that TPS51640RSLR is sourced from the original manufacturer or authorized distributors?
All TPS51640RSLR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS51640RSLR meets industry standards.
7.What is the process for return or replacement of TPS51640RSLR?
All TPS51640RSLR units undergo pre-shipment inspection (PSI). If there is an issue with TPS51640RSLR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS51640RSLR part is unused and in its original packaging.
Return procedure for TPS51640RSLR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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