Texas Instruments TPS51650RSLR
- Part No.:
- TPS51650RSLR
- Manufacturer:
- Texas Instruments
- Category:
- Special Purpose Regulators
- Package:
- 48-VFQFN Exposed Pad
- Datasheet:
-
TPS51650RSLR.pdf
- Description:
- IC REG CTRLR IMVP-7 2OUT 48VQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TPS51650RSLR from Texas Instruments is a dual-channel IMVP-7-compliant step-down controller with integrated FET drivers, supporting 3-phase CPU and 2-phase GPU power delivery. It features D-CAP+™ control architecture, 8-bit DAC (0.250–1.52 V), SVID interface, and integrated overshoot/undershoot reduction (OSR/USR) for Intel VCORE applications.
For engineers reviewing the TPS51650RSLR datasheet, TPS51650RSLR pinout, TPS51650RSLR application, or TPS51650RSLR equivalent, key selection criteria include IMVP-7 compliance, dual-channel phase configuration (3+2), integrated gate drivers, thermal monitoring via CTHERM/GTHERM, and programmable slew rate and current limits.
Technical Context
The TPS51650RSLR implements a D-CAP+™ architecture with overlapping pulse support to minimize output capacitance while delivering fast transient response. Its CPU channel supports one-, two-, or three-phase operation; GPU channel supports one- or two-phase configurations - both fully compliant with Intel IMVP-7 timing, voltage positioning, and digital current monitor requirements.
It integrates two high-current FET gate drivers (CDH1/CDL1, CDH2/CDL2) for CPU phases 1 and 2, while relying on an external TPS51601 driver for CPU phase 3 and both GPU phases. The controller uses separate feedback loops (CVFB/GVFB), independent OCP settings (COCP-R/GOCP-R), and dual PGOOD outputs (CPGOOD/GPGOOD) for system-level fault isolation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Channel Phases | Configurable 1/2/3-phase operation for Intel VCORE rail; enables scalable power delivery up to 94 A in 3-phase mode. |
| GPU Channel Phases | Configurable 1/2-phase operation for Intel VGFX rail; supports up to 46 A in 2-phase mode. |
| DAC Output Range | 8-bit SVID DAC: 0.250 V to 1.52 V in 5-mV steps - meets IMVP-7 VID code resolution and voltage positioning accuracy. |
| Input Voltage Range | 3 V to 28 V conversion range - compatible with adapter, battery, NVDC, and 3/5/12-V input rails. |
| Operating Temperature | –10°C to +105°C ambient rating - qualified for mobile and thin-client platform thermal environments. |
| Package | 48-pin QFN (6 mm × 6 mm, PowerPAD™) - thermally enhanced for high-current VR applications with low θJCbot (2.1°C/W). |
| Integrated Drivers | Two internal N-channel FET drivers (CDH1/CDL1, CDH2/CDL2) with RDRVH ≤ 2.5 Ω and IDRVL ≥ 6 A sink capability. |
Pinout & Package
TPS51650RSLR is housed in a thermally enhanced 48-pin QFN (RSL package) with exposed PowerPAD™ for efficient heat dissipation. Pin assignment follows TI's standard layout for dual-channel IMVP-7 controllers, with dedicated CPU/GPU sense, drive, feedback, and SVID I/O groups.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CDH1 / CDL1 | CPU Phase 1 gate drive outputs | High-side (CDH1) and low-side (CDL1) PWM outputs driving external N-FETs; 2.2-A source/sink capability ensures fast switching. |
| CDH2 / CDL2 | CPU Phase 2 gate drive outputs | Second set of complementary gate drives; enables balanced 2- or 3-phase operation with AutoBalance™ phase balancing. |
| CPWM3 | CPU Phase 3 PWM control | 5-V logic-level output to drive external TPS51601 for third CPU phase - preserves flexibility without adding internal driver complexity. |
| GPWM1 / GPWM2 | GPU Phase 1/2 PWM control | 5-V logic outputs to drive external TPS51601 for both GPU phases - decouples GPU scalability from CPU channel resources. |
| CVFB / GVFB | CPU/GPU voltage feedback inputs | Direct VCORE/VGFX sensing points with soft-stop transistor on CVFB; 20–40 µA bias current enables precision closed-loop regulation. |
| COCP-R / GOCP-R | CPU/GPU overcurrent threshold | Resistor-programmable per-phase valley current limit (4.6–49 mV range); also sets OSR/USR thresholds for dynamic transient suppression. |
| CTHERM / GTHERM | CPU/GPU thermal sensor inputs | NTC thermistor interfaces with VREF divider; supports IMVP-7 thermal bit mapping (755–430 mV) for VR_HOT assertion. |
| VCLK / VDIO | SVID bus interface | 1-V logic-level clock and bidirectional data lines - compliant with IMVP-7 SVID timing, including 100-ns VR_ON debounce and ALERT interrupt signaling. |
Key Features
| Feature | Design Value |
|---|---|
| D-CAP+™ Control Architecture | Enables zero external compensation, fast load-transient response (<10 µs), and minimal output capacitance - reduces BOM count and PCB area. |
| AutoBalance™ Phase Balancing | Internal current-sharing algorithm maintains ≤±3% phase current mismatch across CPU phases - improves thermal distribution and reliability. |
| VCORE Overshoot/Undershoot Reduction | Programmable OSR/USR thresholds (via COCP-R/GOCP-R) actively suppress voltage excursions during load transients - meets IMVP-7 ±3% VCORE tolerance. |
| Adjustable Slew Rate & Soft-Stop | SLEWA pin selects 7 discrete slew rates (1.25–26 mV/µs); soft-stop discharges VCORE through CVFB transistor - prevents reverse current and protects CPU. |
| Dual Independent IMVP-7 Feature Set | Full SVID register map, VR_HOT, ALERT, dual PGOOD, digital current monitor, and PS state management for both CPU and GPU channels - eliminates need for secondary controllers. |
Applications
| Mobile Thin Clients | Gaming Laptops |
|---|---|
Use Scenario: Dual-core or quad-core Intel Core i5/i7 processors in fanless or low-profile notebooks requiring adaptive power states and thermal throttling. IC Role / Device Role / Timing Role: Primary VCORE controller managing CPU voltage scaling, PS state transitions (PS0–PS3), and real-time current monitoring via SVID. Use Value: Enables IMVP-7-compliant dynamic voltage/frequency scaling with <5-µs transient response and 0.25-V minimum output - critical for burst-workload efficiency. | Use Scenario: High-performance discrete GPUs (e.g., NVIDIA GeForce RTX series) co-located with CPU on shared motherboard, demanding independent but synchronized power delivery. IC Role / Device Role / Timing Role: Dedicated VGFX controller delivering 2-phase power with independent OCP, thermal monitoring, and PS management - coordinated with CPU channel via shared SVID bus. Use Value: Supports GPU-specific power states (e.g., G0–G3) and dynamic VID updates at 2-µs latency - sustains frame-rate stability under variable rendering loads. |
| Ultrabooks with Integrated Graphics | Workstation-Class Convertibles |
Use Scenario: Intel Core processors with Iris Xe graphics where CPU and GPU share VR resources but require independent voltage positioning and current limiting. IC Role / Device Role / Timing Role: Single-chip solution providing 3-phase CPU and 2-phase GPU rails with shared SVID interface, dual PGOOD, and independent droop gain tuning (CCOMP/GCOMP). Use Value: Reduces component count by consolidating two VR controllers into one IC - lowers bill-of-materials cost and simplifies layout for space-constrained designs. | Use Scenario: 2-in-1 devices with active cooling and extended battery life requirements, needing robust thermal protection and adaptive power delivery across usage modes. IC Role / Device Role / Timing Role: Dual-rail controller with CTHERM/GTHERM inputs feeding IMVP-7 thermal registers and triggering VR_HOT/ALERT asserts before junction temperature exceeds 155°C. Use Value: Provides hardware-enforced thermal shutdown with 20°C hysteresis - prevents sustained overtemperature operation during sustained compute workloads. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel IMVP-7 VR controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS59650RSLR | Wider operating temperature range (–40°C to +105°C) and extended thermal bit resolution; identical pinout and feature set. | Required for industrial or automotive-adjacent platforms with sub-zero cold-start requirements. | Select TPS59650RSLR when ambient operating temperature may fall below –10°C - otherwise TPS51650RSLR suffices for commercial mobile platforms. |
| ISL95831IRZ | Single-channel IMVP-7 controller (CPU-only); no GPU channel or integrated GPU drivers; requires external GPU controller. | Used in cost-sensitive designs where GPU is integrated and powered from CPU rail or omitted entirely. | Choose ISL95831IRZ only if GPU power delivery is handled separately - TPS51650RSLR provides true dual-rail integration unavailable in single-channel alternatives. |
Compared with TPS59650RSLR, the TPS51650RSLR offers identical functionality at lower cost for commercial-temperature applications, while ISL95831IRZ lacks GPU channel support entirely - making TPS51650RSLR the only drop-in solution for full IMVP-7 dual-rail systems requiring 3+2 phase capability.
Availability
TPS51650RSLR is available at Aetrix Electronics and suitable for mobile computing, ultrabook, and thin-client platforms requiring stable component supply, IMVP-7 compliance, and dual-rail power management.
Supply support for TPS51650RSLR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies with over 50 years of innovation in power conversion ICs.
The TPS51650RSLR belongs to TI's IMVP-7 VR controller product line, engineered specifically for Intel-based mobile platforms requiring high-efficiency, multi-phase CPU/GPU voltage regulation with full SVID protocol support.
FAQ
What is the primary function of the TPS51650RSLR in a laptop power system?
The TPS51650RSLR serves as a dual-channel IMVP-7-compliant step-down controller that independently regulates both the CPU VCORE (3-phase) and GPU VGFX (2-phase) rails. It integrates gate drivers for two CPU phases, communicates via SVID with the processor, and manages dynamic voltage scaling, thermal protection, and power-state transitions - all within a single 48-pin QFN package.
Does the TPS51650RSLR support full IMVP-7 compliance including VR_HOT and ALERT signals?
Yes, the TPS51650RSLR fully implements the IMVP-7 specification: it generates VR_HOT (pin 21) and ALERT (pin 19) open-drain outputs with 1-ms deglitching, supports all required SVID commands (SetVID, SetPS, ReadIMON), and provides dual PGOOD (CPGOOD/GPGOOD) with programmable thresholds - all verified per SLUSAV7 datasheet timing and electrical specs.
How does the TPS51650RSLR handle phase balancing between CPU power stages?
The TPS51650RSLR implements AutoBalance™ phase balancing using internal current-sense amplifiers (ACSINT = 12.00 V/V) and comparator circuitry to maintain ≤±3% current mismatch across CPU phases. This is achieved without external balancer ICs or complex layout constraints - confirmed by IBAL_TOL specification and typical characteristics in Figures 7–10 of the datasheet.
Can the TPS51650RSLR operate without an external FET driver for all three CPU phases?
No. The TPS51650RSLR integrates drivers only for CPU phases 1 and 2 (CDH1/CDL1, CDH2/CDL2). CPU phase 3 requires an external driver - typically the TPS51601 - connected via CPWM3. This architecture allows optimized thermal distribution and scalability while retaining internal drive capability for the highest-current phases.
What is the role of the SLEWA pin on the TPS51650RSLR and how is it configured?
The SLEWA pin (pin 22) sets both VCORE slew rate and soft-stop behavior: a resistor-to-GND selects one of seven discrete slew rates (1.25–26 mV/µs), and the same voltage level latches soft-start/soft-stop timing (SLSTRTSTP = 1.25–1.75 mV/µs). This single-pin configuration simplifies design while meeting IMVP-7 voltage ramping requirements across all power states.
TPS51650RSLR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- D-CAP+™
- Package/Case:
- 48-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Controller, Intel IMVP-7
- Voltage - Input:
- 3V ~ 28V
- Number of Outputs:
- 2
- Voltage - Output:
- 0.25V ~ 1.52V
- Operating Temperature:
- -10°C ~ 105°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-VQFN (6x6)
TPS51650RSLR FAQ
1.How can I place an order for TPS51650RSLR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS51650RSLR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS51650RSLR reliable?
The price and inventory of TPS51650RSLR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS51650RSLR is usually 5 days.
3.What payment methods are accepted for TPS51650RSLR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS51650RSLR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS51650RSLR?
TPS51650RSLR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS51650RSLR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS51650RSLR?
For technical support, including TPS51650RSLR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS51650RSLR requirements.
6.How does Aetrix verify that TPS51650RSLR is sourced from the original manufacturer or authorized distributors?
All TPS51650RSLR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS51650RSLR meets industry standards.
7.What is the process for return or replacement of TPS51650RSLR?
All TPS51650RSLR units undergo pre-shipment inspection (PSI). If there is an issue with TPS51650RSLR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS51650RSLR part is unused and in its original packaging.
Return procedure for TPS51650RSLR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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