Texas Instruments TPS53321RGTR
- Part No.:
- TPS53321RGTR
- Manufacturer:
- Texas Instruments
- Package:
- 16-VFQFN Exposed Pad
- Datasheet:
-
TPS53321RGTR.pdf
- Description:
- IC REG BUCK ADJ 5A 16VQFN
- Quantity:
- Payment:

- Shipping:

Inventory:4,448
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TPS53321RGTR from Texas Instruments is a 5-A synchronous step-down DC/DC regulator with integrated high- and low-side N-channel MOSFETs, 1.1-MHz fixed-frequency voltage-mode control, 2.9 V to 6 V input range, and adjustable 0.6 V to 0.84 × VIN output. It delivers up to 5 A continuous current in a 3 mm × 3 mm QFN package and supports all-MLCC output designs for compact point-of-load applications in computing and digital consumer systems.
For engineers reviewing the TPS53321RGTR datasheet, TPS53321RGTR pinout, TPS53321RGTR application, or TPS53321RGTR equivalent, key selection criteria include its 96% peak efficiency, SmoothPWM™ auto-skip Eco-Mode™ for light-load optimization, master/slave interleaving capability, internal boot switch, and robust protection suite (OCP, OVP, UVP, OTP, soft-stop discharge).
Technical Context
The TPS53321RGTR implements voltage-mode PWM control with a 1.1-MHz nominal switching frequency and supports five configurable operation modes-FCCM master/slave, diode emulation (DE), and high-efficiency (HEF)-selected via the PS pin resistor network. Its integrated power stage features 24 mΩ (3.3-V IN) / 19 mΩ (5-V IN) RDS(on) MOSFETs and an internal bootstrap switch, eliminating external high-side gate drive components.
It provides real-time monitoring of FB voltage against ±17% reference thresholds for power-good (PGD), overvoltage (OVP), and undervoltage (UVP) detection, with 1.2-ms PGD startup delay and 10-µs fault response. Thermal shutdown activates at 140°C with 40°C hysteresis, and overcurrent protection includes dual-path sensing (6.5-A high-side hiccup, 6.8-A low-side immediate latch-off).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Current | Continuous 5-A load capability enables single-chip supply for mid-power SoCs and FPGAs. |
| Input Voltage Range | 2.9 V to 6 V supports direct connection to common intermediate rails (3.3 V, 5 V) without pre-regulation. |
| Output Voltage Range | 0.6 V to 0.84 × VIN allows precise low-voltage core regulation (e.g., 1.5 V @ 3.3-V IN) with adaptive scaling. |
| Switching Frequency | 1.1 MHz (±11%) enables compact magnetics and EMI filtering while maintaining >90% efficiency down to 100 mA. |
| Efficiency | 96% peak efficiency; >90% at 100 mA (VIN = 5 V, VOUT = 1.5 V) due to SmoothPWM™ skip mode and low RDS(on). |
| Protection Features | OCP (6.5-A hiccup / 6.8-A latch), OVP/UVP (±17% VREF), OTP (140°C with 40°C hysteresis), soft-stop discharge (60-Ω internal switch). |
| Package | 3 mm × 3 mm, 16-pin QFN (RGT) with exposed thermal pad ensures low θJA = 42.8°C/W for high-power density layouts. |
Pinout & Package
TPS53321RGTR uses a 3 mm × 3 mm, 16-pin QFN package (RGT) with exposed thermal pad (Pin 17). Pin functions are validated per TI SLUSAF3A datasheet Rev. November 2016.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 EN | Enable input | Active-high logic with 1.35-MΩ internal pull-up; asserts UVLO if <1.1 V; initiates soft-start on rising edge. |
| 2 SYNC | Synchronization I/O | Bidirectional; master outputs 180° out-of-phase signal to slave; accepts external clock ±20% of 1.1 MHz. |
| 3 PGD | Open-drain power-good flag | Asserts high when FB is 83–117% of 0.6-V reference; requires external pull-up; delayed 1.2 ms after valid FB. |
| 4 VBST | Bootstrap supply | Connects external capacitor to SW; powers high-side gate driver; supports >2.4 V VVBST–VSW margin in DE/HEF modes. |
| 5,6,7 SW | Power switch node | Three parallel connections to internal high/low-side MOSFETs and inductor; reduces trace inductance and thermal resistance. |
| 8 PS | Mode configuration input | 10-µA current source; resistor-to-GND selects FCCM/DE/HEF and master/slave role (e.g., 174 kΩ = DE master). |
| 9 COMP | Error amplifier compensation | Type III compensation node; connects RC network to stabilize loop across full load and line ranges. |
| 10 FB | Voltage feedback input | Monitors resistive divider output; sets VOUT = 0.6 V × (1 + R1/R2); also triggers OVP/UVP/PGD thresholds. |
| 11 AGND | Analog ground reference | Separate low-noise return for error amp, reference, and bias circuits; must be tied to PGND at single point. |
| 12 VDD | Analog bias supply | 2.9–3.5 V input powering internal analog circuitry; has dedicated UVLO (2.8 V, 75-mV hysteresis). |
| 13,14 VIN | Power conversion input | Dual inputs for high-current path; connect directly to bulk input capacitor; support 2.9–6 V conversion range. |
| 15,16 PGND | Power ground terminals | Two dedicated low-impedance returns for MOSFETs and SW node; must connect to thermal pad and PCB ground plane. |
Key Features
| Feature | Design Value |
|---|---|
| SmoothPWM™ Auto-Skip Eco-Mode™ | Enables discontinuous conduction (DCM) at light loads to reduce switching loss, achieving >90% efficiency at 100 mA. |
| Master-slave interleaved operation | Reduces input/output ripple by 50% and improves thermal distribution when two TPS53321RGTR devices are synchronized. |
| All-MLCC output capacitor support | Eliminates electrolytic capacitors; enables compact, reliable, low-ESR/ESL output filtering using only ceramic capacitors. |
| Internal boot strap switch | Removes need for external bootstrap diode or charge pump; simplifies layout and improves reliability in high-duty-cycle applications. |
| Prebias start-up capability | Allows safe startup into precharged output rail without reverse current flow; critical for hot-swap and multi-rail sequencing. |
| Soft-stop output discharge | Internally discharges VOUT through 60-Ω switch when EN is low (VIN >1 V), preventing floating outputs during disable. |
Applications
| Server CPU Core Supply | Network Switch ASIC Rail |
|---|---|
Use Scenario: Providing 1.2-V/4.5-A core voltage to x86 CPU in 1U rack server with strict thermal and space constraints. IC Role / Device Role / Timing Role: Primary synchronous buck regulator with voltage-mode control, delivering regulated core power under dynamic load transients. Use Value: 96% peak efficiency and 90% light-load efficiency reduce system heat dissipation; 3 mm × 3 mm QFN enables dense VRM layout near CPU socket. | Use Scenario: Generating 1.0-V/5-A supply for 28-nm network switch ASIC requiring low noise and fast transient response. IC Role / Device Role / Timing Role: Point-of-load regulator with programmable operation mode (HEF for efficiency, FCCM for EMI control) and PGD sequencing. Use Value: Adjustable 0.6–0.84×VIN output range supports ASIC-specific core voltages; internal OCP/OVP/OTP ensures robust field operation. |
| Industrial PLC I/O Module | Embedded GPU Memory Rail |
Use Scenario: Powering isolated 3.3-V/3-A digital I/O bank in industrial programmable logic controller with wide ambient temperature range. IC Role / Device Role / Timing Role: Input-stage buck converter accepting 5-V backplane rail and delivering stable 3.3-V output with tight line/load regulation. Use Value: –40°C to 85°C operating range and 42.8°C/W θJA ensure reliability in uncooled enclosures; all-MLCC design resists vibration and aging. | Use Scenario: Supplying 1.35-V/4.8-A GDDR6 memory interface in automotive infotainment head unit with EMI-sensitive RF coexistence. IC Role / Device Role / Timing Role: High-efficiency, low-noise buck regulator supporting forced CCM mode to fix switching frequency and simplify EMI filter design. Use Value: FCCM mode eliminates frequency variation; 1.1-MHz operation allows small 1-µH inductor; soft-start prevents inrush into large memory capacitor banks. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS53355RGLR | Higher 6-A rating, 1.5-MHz switching, enhanced current-sense accuracy, no PS pin for mode selection. | Targeted at higher-current, higher-frequency designs where 5-A headroom is insufficient. | Select TPS53355RGLR when output current exceeds 5 A or when tighter current-sense tolerance (<±5%) is required. |
| MP2315GJ-Z | Monolithic 6-A buck, 2.2-MHz fixed frequency, no SYNC/PS pins, lower 2.5-V min input, no master/slave support. | Optimized for ultra-compact, cost-sensitive consumer applications with simpler feature set. | Choose MP2315GJ-Z for space-constrained designs needing minimal external components and no interleaving capability. |
Compared with TPS53321RGTR, TPS53355RGLR offers higher current and precision but lacks flexible mode control, while MP2315GJ-Z trades configurability and thermal performance for integration and footprint reduction-making TPS53321RGTR optimal for balanced 5-A PoL designs requiring efficiency, protection, and synchronization.
Availability
TPS53321RGTR is available at Aetrix Electronics and suitable for server CPU core supplies, network switch ASIC rails, and industrial PLC I/O modules requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for TPS53321RGTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in high-efficiency DC/DC conversion.
The TPS533xx family is designed for high-density, high-efficiency point-of-load regulation in computing, networking, and industrial systems-emphasizing integration, thermal performance, and robust protection for mission-critical power rails.
FAQ
What is the maximum output current capability of the TPS53321RGTR?
The TPS53321RGTR delivers continuous 5-A output current under recommended operating conditions (TA ≤ 85°C, proper layout and thermal management). Its overcurrent protection triggers at 6.5 A (hiccup) and 6.8 A (immediate latch-off), ensuring safe operation within this rated limit. Derating is required above 85°C ambient per the device's thermal metrics (θJA = 42.8°C/W).
Does the TPS53321RGTR support prebias start-up?
Yes, the TPS53321RGTR supports prebias start-up, allowing it to safely regulate into an already charged output rail without forcing reverse current. This behavior is enabled by internal circuitry that monitors SW node voltage during enable assertion and disables low-side FET turn-on until the output reaches regulation. Prebias operation is confirmed in the SLUSAF3A datasheet Figure 10.
How does the PS pin configure operation modes on the TPS53321RGTR?
The PS pin on the TPS53321RGTR sources a 10-µA current and selects among five modes via resistor-to-ground: GND = FCCM slave, 24.3 kΩ = DE slave, 57.6 kΩ = HEF mode, 174 kΩ = DE master, and floating/pulled-high = FCCM master. Each setting determines conduction mode (CCM vs DCM), skip behavior, and master/slave synchronization capability as defined in Table 1 of the datasheet.
What is the purpose of the three SW pins on the TPS53321RGTR?
TPS53321RGTR integrates three parallel SW pins (Pins 5, 6, 7) to minimize parasitic inductance and thermal resistance in the high-current power loop connecting internal MOSFETs to the external inductor. This layout reduces voltage spikes during switching transitions, improves efficiency, and enhances thermal performance-especially critical for 5-A continuous operation in the 3 mm × 3 mm QFN package.
Can the TPS53321RGTR be synchronized to an external clock?
Yes, the TPS53321RGTR's SYNC pin accepts an external clock signal within ±20% of its nominal 1.1-MHz switching frequency (i.e., 0.88–1.32 MHz). The falling edge of the external SYNC signal triggers the rising edge of the internal PWM, enabling precise timing alignment in multi-phase or noise-sensitive systems. This capability is documented in the Pin Functions table and Section 7.3.9 of the SLUSAF3A datasheet.
TPS53321RGTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- SmoothPWM™, Eco-Mode™
- Package/Case:
- 16-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.9V
- Voltage - Input (Max):
- 6V
- Voltage - Output (Min/Fixed):
- 0.6V
- Voltage - Output (Max):
- 5.04V
- Current - Output:
- 5A
- Frequency - Switching:
- 1.1MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-VQFN (3x3)
TPS53321RGTR FAQ
1.How can I place an order for TPS53321RGTR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS53321RGTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS53321RGTR reliable?
The price and inventory of TPS53321RGTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS53321RGTR is usually 5 days.
3.What payment methods are accepted for TPS53321RGTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS53321RGTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS53321RGTR?
TPS53321RGTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS53321RGTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS53321RGTR?
For technical support, including TPS53321RGTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS53321RGTR requirements.
6.How does Aetrix verify that TPS53321RGTR is sourced from the original manufacturer or authorized distributors?
All TPS53321RGTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS53321RGTR meets industry standards.
7.What is the process for return or replacement of TPS53321RGTR?
All TPS53321RGTR units undergo pre-shipment inspection (PSI). If there is an issue with TPS53321RGTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS53321RGTR part is unused and in its original packaging.
Return procedure for TPS53321RGTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TPS53321RGTR Tags

-
TPS562201DDCR
Texas Instruments

-
MC34063ABD-TR
STMicroelectronics

-
TPS561201DDCR
Texas Instruments

-
MC33063ADR
Texas Instruments

-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments

-
AP3012KTR-G1
Diodes Incorporated

-
TLV61048DBVR
Texas Instruments

-
AZ34063UMTR-G1
Diodes Incorporated

-
TPS562200DDCR
Texas Instruments

-
AP62300TWU-7
Diodes Incorporated

-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
