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Texas Instruments TPS53513RVER
- Part No.:
- TPS53513RVER
- Manufacturer:
- Texas Instruments
- Package:
- 28-VFQFN Exposed Pad
- Datasheet:
-
TPS53513RVER.pdf
- Description:
- IC REG BUCK ADJ 8A 28VQFN
- Quantity:
- Payment:
- Shipping:
Inventory:1,603
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Product details
Overview
TPS53513 from Texas Instruments is a single-channel synchronous step-down DC-DC converter with D-CAP3™ adaptive on-time control, integrated 13.8-mΩ high-side and 5.9-mΩ low-side MOSFETs, 8-A continuous output current capability, 0.6-V ±0.5% reference voltage, and 0.6-V to 5.5-V programmable output voltage range. It serves as a compact, high-efficiency POL regulator for FPGA, DSP, and ASIC core supplies.
For engineers reviewing the TPS53513 datasheet, TPS53513 pinout, TPS53513 application, or TPS53513 equivalent, key selection considerations include its 28-pin VQFN-CLIP package, eight selectable switching frequencies (250 kHz–1 MHz), FCCM/auto-skip mode flexibility, pre-bias start-up support, and integrated 5-V VREG LDO for gate drive biasing.
Technical Context
The TPS53513 implements D-CAP3™ control using emulated current sensing-eliminating external compensation components-and adapts on-time dynamically to maintain stable frequency across input/output voltage variations. Its internal 5-V VREG LDO powers analog circuitry and the high-side gate driver via the VBST rail.
It supports dual operating modes: forced continuous conduction mode (FCCM) for tight ripple and regulation in performance-critical loads, and auto-skipping Eco-mode™ for >90% efficiency at light loads. Overcurrent protection uses valley-current sensing via the TRIP pin with user-programmable threshold (6.2–9.8 A typical).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 1.5 V to 18 V conversion input; 4.5 V to 25 V VDD bias supply - enables wide-system compatibility including 12-V intermediate bus and 5-V auxiliary rails. |
| Output Current | 8-A continuous - sufficient for mid-tier FPGA I/O banks or dual-core processor cores without external current sharing. |
| Reference Voltage | 600 mV ±0.5% at 25°C - enables precise 0.6-V to 5.5-V output setting with <±1% total output error over temperature and line/load. |
| Switching Frequency | 250 kHz to 1 MHz (8 settings via RF pin resistor divider) - allows optimization of size (higher fSW → smaller inductor) vs. efficiency (lower fSW → lower switching loss). |
| Control Mode | D-CAP3™ with adaptive on-time - delivers sub-10-µs load-step response without loop compensation, ideal for dynamic digital loads. |
| Package | 28-pin VQFN-CLIP (4.5 mm × 3.5 mm) with exposed thermal pad - provides low thermal resistance (RθJC(bot) = 2.2°C/W) for high-power density PCB layouts. |
| Protection Features | OVP/UVP, thermal shutdown (140°C), valley OCP (programmable via TRIP), and open-drain PGOOD - ensures robust operation in unattended embedded systems. |
Pinout & Package
The TPS53513 is housed in a 4.5 mm × 3.5 mm, 28-pin VQFN-CLIP package with an exposed thermal pad for enhanced heat dissipation. Pin numbering follows standard top-view orientation with Pin 1 at top-left corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RF | Frequency configuration input | Resistor-divider connection to VREG/GND sets one of eight switching frequencies (250 kHz–1 MHz); critical for EMI tuning and inductor sizing. |
| FB | Feedback input | Connects to resistor divider from VOUT to PGND; senses output voltage for regulation; 600-mV reference enables accurate scaling. |
| PGOOD | Open-drain power-good output | Asserts high after FB stabilizes within ±8% of target; 2-µs fault response enables system sequencing and fault logging. |
| EN | Enable input | Active-high logic input (1.3–1.5 V threshold); controls startup/shutdown sequencing and power-rail coordination. |
| MODE | Operation mode select | Configures FCCM (low ripple) or auto-skip (high light-load efficiency); also sets D-CAP3 ramp coefficient. |
| VBST | Bootstrap supply | Connects bootstrap capacitor between VBST and SW; powers high-side gate driver; internally tied to VREG via PMOS switch. |
| VREG | 5-V LDO output | Supplies internal analog circuitry and gate drivers; can power external bias rails; regulated 4.65–5.45 V at 200-mA max. |
| VO | VOUT sense input | Direct connection to output node; used for accurate remote sensing and fast transient response in high-current paths. |
| TRIP | OCP threshold setting | Sinks 10 µA; external resistor sets valley-current limit (e.g., 34.8 kΩ → 8-A typical); enables precise overcurrent tailoring. |
| SW | Switch node | High-frequency switching output (up to 1 MHz); connects to inductor; requires low-inductance layout and ceramic capacitor placement. |
| VIN / PGND / GND / GND1 / GND2 | Power and ground terminals | Multiple VIN pins reduce IR drop; 7 PGND pins and 3 GND pins ensure low-impedance return paths for power and signal grounds. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated MOSFETs | 13.8-mΩ high-side + 5.9-mΩ low-side RDS(on) - eliminates external FETs and drivers, reducing BOM count and layout area by >30%. |
| All-ceramic capacitor support | No ESR requirement for output capacitors - enables use of compact, low-profile X5R/X7R MLCCs instead of bulky electrolytics or POSCAPs. |
| Pre-biased start-up | Supports powered-up output rails (e.g., hot-swap or backup supplies) - prevents reverse current flow and ensures glitch-free enable sequencing. |
| Built-in output discharge | Active VO discharge path (10–15 mA sink) - clears residual charge during shutdown, meeting strict power-rail sequencing requirements. |
| Thermal pad design | Exposed copper thermal pad with 2.2°C/W junction-to-case (bottom) resistance - enables >6 W dissipation in 1-in² layout with 2 oz copper. |
Applications
| Server and Cloud-Computing POLs | Broadband Infrastructure Power |
|---|---|
Use Scenario: Regulating 1.2-V core voltage for dual-core ARM-based baseband processors in 5G radio units. IC Role / Device Role / Timing Role: Primary point-of-load converter delivering up to 8 A with <10-µs transient response to handle bursty packet processing loads. Use Value: D-CAP3™ control maintains ±1% output regulation during 6-A load steps, eliminating need for external compensation and reducing design cycle time. | Use Scenario: Powering 3.3-V I/O banks of high-speed SerDes transceivers in optical line cards. IC Role / Device Role / Timing Role: Secondary POL regulator with FCCM mode enabled to suppress switching noise below 100 kHz and prevent interference with 25+ Gbps data lanes. Use Value: 250-kHz minimum switching frequency and ultra-low output ripple (<10 mVpp) meet stringent jitter-sensitive power integrity specs. |
| FPGA Core Supply | Industrial Embedded Controller |
Use Scenario: Generating 0.85-V VCCINT for Xilinx Artix-7 FPGA in programmable logic controllers. IC Role / Device Role / Timing Role: High-accuracy buck controller with 0.6-V ±0.5% reference and remote VO sensing for millivolt-level core voltage stability. Use Value: Tight reference tolerance and built-in soft-start (1-ms ramp) prevent FPGA configuration failure during cold start or brownout recovery. | Use Scenario: Providing 1.8-V and 3.3-V rails for ARM Cortex-M7 microcontrollers and CAN transceivers in factory automation gateways. IC Role / Device Role / Timing Role: Dual-rail POL solution using single TPS53513 per rail with independent feedback and mode control. Use Value: Auto-skip Eco-mode™ achieves >88% efficiency at 50-mA load, extending uptime in battery-backed or energy-harvested edge nodes. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS53355RGT | 4.5-V to 25-V input; 3-A output; 3-mm × 3-mm QFN-16; no VREG LDO or TRIP pin | Targeted at lower-current, space-constrained apps (e.g., portable instrumentation); lacks programmable OCP and integrated gate-drive bias | Select when output current ≤3 A and board area is premium; not suitable for 8-A FPGA core rails. |
| MP2315GJ-Z | 4.5-V to 26-V input; 6-A output; 2-mm × 3-mm QFN-12; fixed 500-kHz fSW; no MODE/FCCM control | Cost-optimized for fixed-frequency consumer power; missing auto-skip, PGOOD, and precision reference | Choose for non-critical 6-A loads where BOM cost outweighs efficiency and transient performance. |
Compared with TPS53513, TPS53355RGT offers smaller footprint but sacrifices 5-A current headroom and critical features like VREG biasing and OCP programming; MP2315GJ-Z reduces size and cost but eliminates FCCM/skip mode selection and precision monitoring - making TPS53513 the only option supporting full-feature 8-A POL design with thermal and sequencing robustness.
Availability
TPS53513 is available at Aetrix Electronics and suitable for server power delivery, 5G infrastructure, FPGA core supplies, and industrial embedded controllers requiring stable component supply and long-term production continuity.
Supply support for TPS53513 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in high-efficiency DC-DC conversion.
The TPS53513 belongs to TI's SWIFT™ synchronous buck converter family, engineered for high-density, high-transient-performance point-of-load regulation in computing, networking, and industrial systems.
FAQ
What is the recommended inductor value for TPS53513 in a 12-V input to 1.2-V output design?
The TPS53513 datasheet specifies 1 µH as the standard inductor value for 12-V input and 1.2-V output at 500 kHz or 1 MHz switching frequency. This value balances peak current ripple (~30% of 8-A full load), core saturation margin, and thermal performance. For FCCM operation, a 1-µH, 2.1-mΩ shielded power inductor (e.g., PCMC135T-1R0MF) is validated in TI's reference design. Lower values increase ripple and stress MOSFETs; higher values reduce ripple but extend transient recovery time.
Does TPS53513 support pre-biased output start-up, and how is it enabled?
Yes, TPS53513 supports pre-biased start-up natively without external components. When the output voltage is already present at the VO pin before EN assertion, the device disables the low-side MOSFET during soft-start and ramps the high-side duty cycle gradually to avoid reverse current flow. This behavior is inherent to the D-CAP3™ control architecture and requires no configuration - confirmed in Figure 29 (Prebias Operation) of the TPS53513 datasheet.
How is overcurrent protection configured on TPS53513, and what is the typical trip threshold?
Overcurrent protection on TPS53513 is configured via the TRIP pin, which sources a precise 10-µA current at room temperature. Connecting an external resistor (e.g., 34.8 kΩ) between TRIP and GND sets the valley-current limit - for that value, the typical OCL threshold is 8.0 A. The datasheet provides a full table (Electrical Characteristics, IOCL row) showing thresholds from 4.2 A to 9.8 A based on resistor selection, enabling application-specific current limiting without hardware changes.
Can TPS53513 operate with only ceramic output capacitors, and what is the minimum required capacitance?
Yes, TPS53513 is explicitly designed for all-ceramic output capacitor operation - no ESR requirement. The minimum recommended output capacitance is 10 × 22 µF (220 µF total) using 1206-size X5R/X7R MLCCs, as validated in the Figure 31 test circuit. This configuration ensures stability across the full 0.6–5.5-V output range and 0–8-A load, eliminating need for tantalum or polymer capacitors and reducing board height and cost.
What is the function of the VREG pin on TPS53513, and can it power external circuitry?
The VREG pin on TPS53513 outputs a regulated 5-V supply (4.65–5.45 V) from an internal LDO powered by VDD. It supplies internal analog blocks and the high-side gate driver via VBST. While rated for 200-mA maximum load, TI recommends limiting external loading to ≤50 mA to maintain regulation accuracy and thermal margin. The TPS53513 datasheet confirms VREG can power small external bias rails (e.g., ADC references or level shifters) if current demand is verified within spec.
TPS53513RVER Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- SWIFT™, D-CAP3™, Eco-Mode™
- Package/Case:
- 28-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 1.5V
- Voltage - Input (Max):
- 18V
- Voltage - Output (Min/Fixed):
- 0.6V
- Voltage - Output (Max):
- 5.5V
- Current - Output:
- 8A
- Frequency - Switching:
- 200kHz ~ 1MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-VQFN-CLIP (4.5x3.5)
TPS53513RVER FAQ
1.How can I place an order for TPS53513RVER through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS53513RVER on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS53513RVER reliable?
The price and inventory of TPS53513RVER are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS53513RVER is usually 5 days.
3.What payment methods are accepted for TPS53513RVER?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS53513RVER transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS53513RVER?
TPS53513RVER orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS53513RVER order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS53513RVER?
For technical support, including TPS53513RVER datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS53513RVER requirements.
6.How does Aetrix verify that TPS53513RVER is sourced from the original manufacturer or authorized distributors?
All TPS53513RVER products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS53513RVER meets industry standards.
7.What is the process for return or replacement of TPS53513RVER?
All TPS53513RVER units undergo pre-shipment inspection (PSI). If there is an issue with TPS53513RVER, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS53513RVER part is unused and in its original packaging.
Return procedure for TPS53513RVER:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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